Commit graph

64699 commits

Author SHA1 Message Date
Bin Meng
ff0fa6c1b3 riscv: Add Kconfig option for SBI v0.2
SBI v0.2 is more scalable and extendable to handle future needs
for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM
extension, only a single hart need to boot and enter operating
system. The booting hart can bring up secondary harts one by one
afterwards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
6fa022e8fc riscv: Add SMP Kconfig option dependency for U-Boot proper
U-Boot proper running in S-mode only need SMP support when using
SBI v0.1. With SBI v0.2 HSM extension, it does not need implement
multicore boot in U-Boot proper.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
191636e448 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
With SBI v0.2 HSM extension, only a single hart need to boot and
enter operating system. The booting hart can bring up secondary
harts one by one afterwards.

For U-Boot running in SPL, SMP can be turned on, while in U-Boot
proper, SMP can be optionally turned off if using SBI v0.2 HSM.

Introduce a new SPL_SMP Kconfig option to support this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
84dc9d2690 riscv: Merge unnecessary SMP ifdefs in start.S
Two consecutive SMP ifdefs blocks can be combined into one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
ed1475e2f4 riscv: qemu: Remove the simple-bus driver for the SoC node
Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a
"riscv-virtio-soc" compatible string, and a "simple-bus" driver
was created to accommodate that special case in U-Boot.

Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus",
hence the special simple-bus driver is no longer needed.

Update the doc to mention the latest tested QEMU version 4.2.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:06 +08:00
Lukas Auer
846b612014 Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"
The commit was added as a workaround required in QEMU when using BBL as
the supervisor binary interface (SBI) for Linux. We are now using
OpenSBI to provide the SBI, the workaround is therefore not required
anymore and can be removed.

This reverts commit 897206c5cc.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:13:35 +08:00
Pragnesh Patel
5988bb9dbf riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:13:23 +08:00
Tom Rini
caad316b31 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- mvebu bubt cmd: Add A38x support (Joel)
- Clearfog: Fix SCSI boot duplication (Joel)
- Armada-37xx: Fix DDR PHY clock divider values (Marek)
2020-04-22 13:00:21 -04:00
Tom Rini
2b63959e30 Merge tag 'mmc-2020-4-22' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- iproc_sdhci memory leak fix and enable R1B resp quirk
- more mmc cmds and several mmc updates from Heinirich
- Use bounce buffer for tmio sdhci
- Alignment check for tmio sdhci
2020-04-22 08:58:41 -04:00
Heinrich Schuchardt
2448c34f9f drivers: mmc: rpmb: do not build for SPL
RPMB support is used by the 'mmc rpmb' command and by the OP-TEE support.
We do not need it in SPL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:57 +08:00
Harald Seiler
c51b751893 spl: mmc: Rename spl_boot_partition() to spl_mmc_boot_partition()
This function is only relevant to the MMC driver so calling it
spl_boot_partition() might be confusing.  Rename it to
spl_mmc_boot_partition() to make its purpose more clear (and bring
it in line with spl_mmc_boot_mode()).

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-22 20:41:57 +08:00
Harald Seiler
e97590654a spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()
The function's name is misleading as one might think it is used
generally to select the boot-mode when in reality it is only used by the
MMC driver to find out in what way it should try reading U-Boot Proper
from a device (either using a filesystem, a raw sector/partition, or an
eMMC boot partition).

Rename it to spl_mmc_boot_mode() to make it more obvious what this
function is about.

Link: https://lists.denx.de/pipermail/u-boot/2020-April/405979.html
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-22 20:41:57 +08:00
Marek Vasut
4a66d4ee33 mmc: tmio: sdhi: Implement get_b_max function
Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit
the b_max per hardware capabilities such that select Gen2 controllers have
16bit block transfer limit, the rest has 32bit block transfer limit and on
Gen3, the block transfer limit on addresses above the 32bit boundary is set
to 1/4 of the malloc area.

Originally, on Gen3, the block transfers above the 32bit area were limited
to PIO only, which resulted in (R8A7795 Salvator-X , HS200 eMMC):
  => time mmc read 0x0000000700000000 0 0x10000
  time: 0.151 seconds
  => time mmc read 0x0000000700000000 0 0x100000
  time: 11.090 seconds
with bounce buffer in place and b_max adjustment in place:
  => time mmc read 0x0000000700000000 0 0x10000
  time: 0.156 seconds
  => time mmc read 0x0000000700000000 0 0x100000
  time: 2.349 seconds

Note that the bounce buffer does mallocate and free the bounce buffer
for every transfer. Experiment which removes this results in further
increase of read speed, from 2.349s to 2.156s per 512 MiB of data,
which is not such a significant improvement anymore. It might however
be interesting to have bounce buffer directly in the MMC core or even
block core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Marek Vasut
145429aac0 mmc: Add option to adjust b_max before long read
Add getter function which permits adjusting the maximum number of
blocks that could be read in a single sustained read transfer based
on the location of the source/target buffer and length, before such
transfer starts.

This is mainly useful on systems which have various DMA restrictions
for different memory locations, e.g. DMA limited to 32bit addresses,
and where a bounce buffer is used to work around such restrictions.
Since the U-Boot bounce buffer is mallocated, it's size is limited
by the malloc area size, and the read transfer to such a buffer must
also be limited. However, as not all areas are limited equally, the
b_max should be adjusted accordinly as needed to avoid degrading
performance unnecessarily.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Marek Vasut
d2661d8e9f mmc: tmio: sdhi: Use bounce buffer to avoid DMA limitations
The R-Car SDHI DMA controller has various restrictions. To work around
those restrictions without falling back to PIO, implement bounce buffer
with custom alignment check function which tests for those limitations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Marek Vasut
80a624f2f0 ARM: rmobile: Increase malloc area size
Increase the malloc area size significantly to cater for bounce buffer
used by the SDHI driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Marek Vasut
8074ffe335 common: bouncebuf: Permit passing custom alignment check function
Add extended version of the bounce_buffer_start(), which permits passing in
a custom alignment checker function for the buffer. This is useful e.g. on
systems with various DMA restrictions and where the checker function might
be more complex than a simple CPU cache alignment check.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Heinrich Schuchardt
453d21381b mmc: adjust Kconfig for mmc sub-commands
All sub-commands of the mmc command should be shown in the Kconfig menu
next to the mmc command. This includes:

* mmc bkops
* mmc rpmb
* mmc swrite

The mmc rpmb sub-command is not usable without CONFIG_SUPPORT_EMMC_RPMB.
Add the missing dependency.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-22 20:41:56 +08:00
Rayagonda Kokatanur
29617ca39a drivers: mmc: iproc_sdhci: move host.mmc init before sdhci_setup_cfg
move host.mmc before sdhci_setup_cfg

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
2020-04-22 20:41:55 +08:00
Rayagonda Kokatanur
7a65b8b6bb drivers: mmc: iproc_sdhci: fix compilation warning
set_ios_post return type changed from void to int, correcting
the same to fix compilation warning.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
2020-04-22 20:41:55 +08:00
Bharat Kumar Reddy Gooty
2bb02b1a81 drivers: mmc: iproc_sdhci: enable broken R1B response quirk
Enable SDHCI_QUIRK_BROKEN_R1B quirk.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-04-22 20:41:55 +08:00
Bharat Kumar Reddy Gooty
d5b8500f03 drivers: mmc: iproc_sdhci: fix possible memory leak
Free the pointer variable 'iproc_sdhci' upon failure to fix
possible memory leak.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-04-22 20:41:55 +08:00
Heinrich Schuchardt
0469d84636 cmd: mmc: provide boot area protection command
Provide command 'mmc wp' to power on write protect boot areas on eMMC
devices.

The B_PWR_WP_EN bit in the extended CSD register BOOT_WP is set. The boot
area are write protected until the next power cycle occurs.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-22 20:41:55 +08:00
Heinrich Schuchardt
d5210e4589 cmd: mmc: display write protect state of boot partition
Boot partitions of eMMC devices can be power on or permanently write
protected. Let the 'mmc info' command display the protection state.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-22 20:41:55 +08:00
Heinrich Schuchardt
1601ea2126 mmc: export mmc_send_ext_csd()
Export function mmc_send_ext_csd() for reading the extended CSD register.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-22 20:41:54 +08:00
Heinrich Schuchardt
9abfe33d10 mmc: EXT_CSD registers for write protection
Add the EXT_CSD register definition related to write protection.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-22 20:41:54 +08:00
Joel Johnson
f60a66ef5d cmd: mvebu: bubt: show image boot device
When a mismatch is found trying to write an image for one boot method
to a different boot device, print an error message including the image
header marked target boot device type.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
549ba7b440 arm: mvebu: clearfog: enable bubt command
With support added for Armada 38x, include the bubt command in
ClearFog defconfig.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
658854a626 cmd: mvebu: bubt: verify A38x target device type
Ensure that the device to which an image is being written includes
header information indicating boot support for the destination
device.

This is derived from the support in the SolidRun master-a38x vendor
fork.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
f41b85ee6a cmd: mvebu: bubt: correct U-Boot spelling
Replace "U-BOOT" text with correct spelling

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
8ec6db7813 cmd: mvebu: bubt: add A38x support
Add support for Armada 38x devices in bubt flashing utility.
This is based on (and streamlined from) the support in the SolidRun
master-a38x vendor fork.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
ab2f757eb0 arm: mvebu: correct SPL boot configs for SPI/MMC
Update mvebu SPL boot selection mechanism for the move to driver model
usage by ensuring that the required driver support for SPI and MMC
booting is available in SPL when the respective boot method is
selected.

Previously, all mvebu boards selected a boot method (implicitly
MVEBU_SPL_BOOT_DEVICE_SPI for many) even if SPL booting wasn't used.
This changes mvebu boot method selection to depend on SPL usage which
resolves the issue with aarch64 boards which don't use SPL getting an
implicit boot device selection resulting in unmet dependencies. The
32-bit arm boards do use SPL, but I'm led to conclude that most aren't
intentionally using the MVEBU_SPL_BOOT_DEVICE selection since none have
SPL_DM_SPI enabled in their defconfig even though they still implicitly
select the SPI boot method.

This also results in the new addition of SPL_GPIO_SUPPORT to helios4.
The mainline dts for helios4 includes the cd-gpios entry for sdhci with
identical addresses as the clearfog dts. I don't have a helios4 board
to confirm, but based on the current source conclude that the board
itself is either wired to pull the signal low for eMMC, or the default
MMC boot isn't fully functional in mainline. In either case, as far as
I can tell, including the GPIO support will at least cause no
regression.

Tested on SolidRun ClearFog devices.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Joel Johnson
36d61a3d0a arm: mvebu: clearfog: adjust SCSI boot duplication
Fix duplication resulting from merging of multiple related series.
Commits cecf38a75, bd02fd29f, and 201a500de added or adjusted SCSI
boot support for ClearFog, but in slightly different locations which
didn't result in a merge conflict.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Marek Behún
239f424f49 clk: armada-37xx-periph: fix DDR PHY clock divider values
Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).

This fixes clk dump reporting DDR PHY clock rate differently from Linux.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Tom Rini
2f2031e647 Various improvements to buildman summary output
-----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAl6e6GgRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreZ5hwf9Eso9WyGKLi32j764EXnCf0XLj6WZ1HiI
 ybk7NABiu9XAg0zfGxX8k3AUdhmMVHSAmLQiATi2rpyXFoyTRVHM5EG6jB8xVpM4
 tc9DBYSGAHSyD+zUQKkc+8aChdN/xAT/32PKe4g6boHnZOXQ0GLZyE4JMsSePC21
 h8sVb5KyTCZfCY503ej+TwTWPgkI2yq5neDAt2SO8v5cXYs6ImgzJbi5hnOACkeA
 G3b9QBGrOWdDMQS7qBdoo5d/JQZ6CCXS3j7FddtEuAa6pebVDmxEk3cuDaxqycK3
 EpZdROERyk9B7uQy6mSEtfeZHxpcaL1OMAhNnPGhRyTSQjRpuY4/XQ==
 =4Z39
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-21apr20' of git://git.denx.de/u-boot-dm

Various improvements to buildman summary output
2020-04-21 17:53:23 -04:00
Tom Rini
bdcb29960e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Backplane support and bug fixes
2020-04-21 15:20:42 -04:00
Simon Glass
b1e5e6d224 buildman: Change the exit codes
The current exit codes of 128 and 129 are useful in that they do not
conflict with those returned by tools, but they are not actually valid.
It seems better to pick some codes which work with 'bit bisect run'.

Update them to 100 (for errors) and 101 (for warnings).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
a38930e227 buildman: Update the TODO items
A few of these have been done. Drop those and add some new ideas.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
113a8a5ff3 buildman: Add an option to ignore migration warnings
These are becoming more common now. They cause boards to show warnings
which can be mistaking for compiler warnings.

Add a buildman option to ignore them. This option works only with the
summary option (-s). It does not affect the build process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
174592b964 buildman: Add an option to ignore device-tree warnings
Unfortunately the plague of device-tree warnings has not lifted. These
warnings infiltrate almost every build, adding noise and confusion.

Add a buildman option to ignore them. This option works only with the
summary option (-s). It does not affect the build process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
eb70a2c059 buildman: Make -I the default
At present buildman defaults to running 'mrproper' on every thread before
it starts building commits for each board. This can add a delay of about 5
seconds to the start of the process, since the tools and other invariants
must be rebuilt.

In particular, a build without '-b', to build current source, runs much
slower without -I, since any existing build is removed, thus losing the
possibility of an incremental build.

Partly this behaviour was to avoid strange build-system problems caused by
running 'make defconfig' for one board and then one with a different
architecture. But these problems were fixed quite a while ago.

The -I option (which disabled mrproper) was introduced four years ago and
does not seem to cause any problems with builds.

So make -I the default and deprecate the option. To allow use of
'mrproper', add a new -m flag.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
ea09fb5bf1 buildman: Update workflow documentation with more detail
Make a few additions and change some wording in the workflow
documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
9e040b5746 buildman: Add the abbreviation for --boards
This option may be frequency used, so mention that it can be abbreviated
to --bo

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
f972836593 buildman: Update the 'theory of operation' a little
Make a few updates to this important section of the documentation, to
make things clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
7b33f21804 buildman: Show a summary of the build result
When buildman finishes it leaves the last summary line visible, which
shows the number of successful builds, builds with warnings and builds
with errors.

It is useful also to see how many builds were done in total along with
the time taken. Show these on a separate line before buildman finishes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
95ed0a2dbf buildman: Limit the length of progress messages
If a progress message is longer than the terminal line it will scroll the
terminal. Limit the messages to the terminal width.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
6eb76cac1c buildman: Show the number of builds remaining
It is nice to see the actual number of builds remaining to complete. Add
this in the progress message, using a different colour.

Drop the unnecessary 'name' variable while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
edae4ad3bc buildman: Drop unused output code
The commit counter is a hangover from when buildman processed each board
for a commit. Now buildman processes each commit for a board, so this
output is never triggered.

Delete it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
212c0b8170 buildman: Show a message when fetching a repo
Fetching updated versions of a repo can take time. At present buildman
gives no indication that it is doing this.

Add a message to explain the delay.

Tidy up a few other messages while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00
Simon Glass
102969bb2c buildman: Drop the line-clearing code in Builder
The new feature in terminal can be used by buildman. Update the Builder
class accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-21 06:33:47 -06:00