The versaclock doesn't have a driver yet, but there are a bunch
of device tree updates for the Beacon RZ/G2 boards that won't
compile without these. A driver is coming, so sync the bindings
for now
Signed-off-by: Adam Ford <aford173@gmail.com>
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
