This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051 ("ARM: mach-mvebu: handle fall-back to UART boot").
So there is no need to define BOOT_FROM_UART_ALT constant and special
handling for it anymore, remove it.
This change effectively revers commit f3a88e2ca1 ("arm: mvebu: fix boot
from UART on ClearFog Base").
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Show correct information in debug() output and use correct names for variables.
No functional change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
If this hooks is needed later, it should be added and populated for
real.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Proper U-Boot moves SPI0 CS0 Flash mapping from 0xD4000000 to 0xF4000000
and change its size from 64 MB to 8 MB. Definitions are already in
MBUS_SPI_BASE/MBUS_SPI_SIZE macros. So define these macros also for SPL
build, use them in env_sf_get_env_addr() function and move this function
from spl.c to cpu.c to be available in Proper U-Boot too.
Signed-off-by: Pali Rohár <pali@kernel.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.
But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222 ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.
The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.
Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.
After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.
To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.
Fixes: 5bb2c550b1 ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
For some unknown reason when L2 cache is disabled on Armada 385 then loadb,
loadx and loady commands do not work with higher baudrates than 115200
(they just abort transfer) and lzmadec command with lzma image of size
0x7000000 (maybe even smaller, we tested this one) is doing decompression
for more than 2 minutes. After enabling L2 cache decompression takes only
30s and loadb, loadx and loady are stable and working fine.
git bisect identified problematic commit 3308933d2f ("arm: mvebu: Avoid
reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit
above issues were not present.
But investigation showed that above issue was possible to reproduce also by
reverting that commit and forcing compiler to do inline optimization of
mvebu_soc_family() function. Which seems that the root of this issue is in
caches and position of instruction of segments. So currently it is unknown
what is or was broken, but code movement, code inlining or other compiler
optimization triggered it.
Commit 3e5ce7ceeb ("arm: mvebu: Enable L2 cache on Armada XP") mentioned
that enabling L2 cache on Armada XP improved performance and that Armada
38x has L2 disabled (which is default state) and if needed it has to be
enabled in separate patch. As enabling L2 cache also improve performance
on Armada 38x, enable it.
Note that Aurora cache in no outer mode is available only on Armada XP,
hence it is not touched for Armada 38x code.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Reported-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada
XP at all") introduced branch for non-AXP code which was guarded by A38X
condition. Fix this issue by checking for AXP platform, not by A38X.
Fixes: c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada XP at all")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID
register too many times") broke support for caches on all Armada SoCs.
Before that commit there was code:
if (mvebu_soc_family() != MVEBU_SOC_A375) {
dcache_enable();
}
And after that commit there is code:
if (IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Comment above this code says that d-cache should be disabled on Armada 375.
But new code inverted logic and broke Armada 375 and slowed down all other
Armada SoCs (including A38x).
Fix this issue by changing logic to:
if (!IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Which matches behavior prior that commit.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Change detection of platform/cpu from runtime to compile time via config
define. This completely eliminates compiling code which is not going to run
on selected platform. Code which parses and prints device / revision id
still reads device id from MVEBU_REG_PCIE_DEVID register, but only once.
Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, like debug_uart_init().
So do it earlier in arch_very_early_init() instead of arch_cpu_init().
Movement is done in proper U-Boot, not in SPL. SPL may return to bootrom
and bootrom requires internal registers at (old) expected location.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This register is referenced in one location and does not seem
configurable, so remove it from CONFIG namespace.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Move the function get_boot_device() from spl.c to cpu.c.
Make it visible, so that it may be used from other files.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:
It's a **mistake** to use typedef for structures and pointers.
Besides, using typedef for structures is annoying when you try to make
headers self-contained.
Let's say you have the following function declaration in a header:
void foo(bd_t *bd);
This is not self-contained since bd_t is not defined.
To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>
#include <asm/u-boot.h>
void foo(bd_t *bd);
Then, the include direcective pulls in more bloat needlessly.
If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:
struct bd_info;
void foo(struct bd_info *bd);
Right, typedef'ing bd_t is a mistake.
I used coccinelle to generate this commit.
The semantic patch that makes this change is as follows:
<smpl>
@@
typedef bd_t;
@@
-bd_t
+struct bd_info
</smpl>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
SPL does not initialize mbus_dram_info. Don't change the ahci mbus
settings of the ROM. This allows the ahci to work in SPL.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This allows the ahci_mvebu driver to do A38x platform specific
configuration at initialization.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The Marvell DDR3 training code is now part of the U-Boot SPL so the
comment saying it needs porting is no longer correct.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a
hardware errata enabling RGMII to work when the Ethernet voltage is
configured to 3.3V.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
This fixes the USB 3.0 support for the a38x SOC.
Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use fdt_addr_t]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.
This commit was created in the following steps.
[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'
[2] create the Kconfig entries in drivers/mmc/Kconfig
[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR
[4] Sort drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Armada 375 still has some problems with d-cache enabled in the ethernet
driver (mvpp2). So lets keep the d-cache disabled until this is solved.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This adds basic support for Marvell's MV78230 SoC which belongs to the
Armada XP series.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
As these structs are local only and const, declare them accordingly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
This is preparation for the runtime bootmode detection in spl.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
With this patch, the CPU and the DDR frequencies will get printed in the
U-Boot startup messages. Resulting in such a log:
U-Boot 2016.01-rc2-00188-gb8eeaec-dirty (Dec 21 2015 - 12:32:35 +0100)
SoC: MV78460-B0 at 1600 MHz
I2C: ready
DRAM: 4 GiB (800 MHz, ECC not enabled)
...
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This is not needed any more since the switch to DM / DTS network
initialization on MVEBU. Lets remove it, as it otherwise leads
to compilation warning when CONFIG_NET is not enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds support for the dual core Armada XP variant, the
MV78260. It has some minor differences to the 4-core MV78460,
e.g. only 12 serdes lanes.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
Use the clrbits() / setbits() functions instead of clrsetbits() when
bit are only cleared or set.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch leaces the cache configuration untouched for the AXP in the
setup done by the BootROM. Resulting in the cache still being enabled
at the startup of U-Boot. This leads to a slightly faster boot to the
U-Boot prompt (or Linux of course).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch removes the call to arch_cpu_init() in the SPL U-Boot version.
As SPL does not need all the configuration done in this function. And
also does not need the reconfiguration of the internal register
address to 0xf1000000. This will be done by the main U-Boot later on.
This also fixes a problem with the timer not beeing initialized on AXP,
as needed for the mdelay in the setup_usb_phys(). This will now only
be called once in main U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
