3 commits

Author	SHA1	Message	Date
Bin Meng	3b621ccabd	x86: Test mtrr support flag before accessing mtrr msr ... On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>	2015-01-23 17:24:55 -07:00
Bin Meng	566d1754d3	x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c ... arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>	2015-01-23 17:24:54 -07:00
Simon Glass	aff2523f69	x86: Add support for MTRRs ... Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>	2015-01-13 07:25:00 -08:00