This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
SPI2_CS0 == 0: NAND (default)
SPI2_CS0 == 1: eMMC
am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
AM437x Starter Kit has a qspi flash and gbit ethernet
support. By muxing those signals, we can use those
interfaces from u-boot.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
