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Author SHA1 Message Date
Fabio Estevam
45156edb16 README.mpc85xx-sd-spi-boot: Suggest the NXP boot format github repo
As explained in the text at the bottom of the page
https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format:

"QUIC repositories on this site will not receive any updates after
March 31, 2022, and will be deleted on March 31, 2023."

Point to the NXP boot format github repo instead.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2023-03-22 12:51:02 -04:00
Pali Rohár
d66b0f5dd7 Fix URLs to old freescale git repos
Freescale git repos are now on source.codeaurora.org.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-03-28 08:22:17 -04:00
York Sun
789460c914 powerpc: P2010: Drop configuration for P2010
P2010 is a single-core version of P2020. There is no P2010 target
configured. Drop related macros. P2010 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
46d9fc0bb7 powerpc: P1014: Drop configuration for P1014
P1014 is a variant of P1010. There is no P1014 target configured.
Drop related macros. P1014 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
2f8b81268a powerpc: P1013: Drop configuration for P1013
P1013 is a single-core version of P1022. There is no P1022 target
configured. Drop related macros. P1022 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
83b9bea116 powerpc: P1012: Drop configuration for P1012
P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
Ying Zhang
bb0dc1084f powerpc: mpc85xx: Support booting from SD Card with SPL
The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
	* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
	ddr spd code can get the interleaving mode setting in env. It loads
	final uboot image from offset 96KB.
	* final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:26 -07:00