4 commits

Author	SHA1	Message	Date
Wolfgang Denk	8e5e9b940c	Coding style cleanup; update CHANGELOG ... Signed-off-by: Wolfgang Denk <wd@denx.de>	2009-07-07 22:35:02 +02:00
Roy Zang	29c3518246	85xx: Add pci e1000 Ethernet support for P2020 board ... Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2009-06-30 08:26:34 -05:00
Kumar Gala	156984a361	8xxx: Fix PCI bus address setup for 36-bit configs ... We want the outbound PCI memory map to end at the 4G boundary so we can maximize the amount of space available for inbound mappings if we have large amounts of memory. This matches the device tree setup in the kernel for the 36-bit physical configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2009-06-30 08:24:22 -05:00
Srikanth Srinivasan	feb7838f97	85xx: Add P2020DS support ... The patch adds support for P2020DS reference platform. DDR3 interface uses hard-coded initialization rather than SPD for now and was tested at 667Mhz. Some PIXIS register definitions and associated code sections need to be fixed. TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all tested under u-boot. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2009-06-12 17:16:25 -05:00