Commit graph

67 commits

Author SHA1 Message Date
Alison Wang
0cbba8e953 ls102xa: fdt: Disable IFC in SD boot for QSPI
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:56 -07:00
Fabio Estevam
f861f51c46 ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.

Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.

This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.

In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.

This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.

Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-12 12:56:32 -04:00
Wang Dongsheng
6f0586e692 armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin table
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.

Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:37 -07:00
Wang Dongsheng
340848b185 arm/ls102xa: Add PSCI support for ls102xa
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.

Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Alison Wang
49a5e42a78 arm: ls1021a: Remove the inappropriate use of the function 'sprintf'
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Jaiprakash Singh
39b0bbbb23 driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
chenhui zhao
9f076be713 arm: ls102xa: workaround for cache coherency problem
The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:59 -08:00
Minghuan Lian
636ef95605 arm/ls102xa: create TLB to map PCIe region
LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.

VA mapping:
    -------  <---- 0GB
   |       |
   |       |
   |-------| <---- 0x24000000
   |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
   |-------| <---- 0x300000000
   |       |
   |-------| <---- 0x34000000
   |///////|  ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
   |-------| <---- 0x40000000
   |       |
   |-------| <---- 0x80000000 DDR0 space start
   |\\\\\\\|
   |\\\\\\\|  ===> 2GB VA map for 2GB DDR0 Memory space
   |\\\\\\\|
   -------  <---- 4GB DDR0 space end

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:31 -08:00
tang yuantian
41ba57d0c7 fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24 09:12:32 -06:00
Alison Wang
33d2e46591 ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
0181937fa3 crypto/fsl: Add fixup for crypto node
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Xiubo Li
290e6e921f ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.

Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:53 -08:00
Alison Wang
86949c2b7c arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:39:22 -08:00
chenhui zhao
306fa01279 arm: ls102xa: clear EPU registers for deep sleep
After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:42 -08:00
Tang Yuantian
b699b01e5c arm: ls102xa: fixed a bus frequency setting error
The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:09 -08:00
Wang Huan
d60a2099a2 arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-08 10:30:32 -07:00