Commit graph

16127 commits

Author SHA1 Message Date
Stefan Roese
cf6eb6da43 ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.

Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-19 15:29:03 +02:00
Scott McNutt
254ab7bd46 nios2: Move individual board linker scripts to common script in cpu tree.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-16 16:12:39 -04:00
Michal Simek
8ff972c6e9 microblaze: Consolidate cache code
Merge cpu and lib cache code.
Flush cache before disabling.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:56:33 +02:00
Michal Simek
9b4d905690 microblaze: Flush cache before jumping to kernel
There is used max cache size on system which doesn't define
cache size.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:04 +02:00
Michal Simek
70524883b0 microblaze: Support system with WB cache
WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.

You need newer toolchain with wdc.flush support.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:02 +02:00
Michal Simek
9769b73f60 microblaze: Change initialization sequence
env_relocation should be called first.
Added stdio_init too.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:56 +02:00
Michal Simek
e6177b36b8 microblaze: Change cache report messages
It is more accurate to show that caches are OFF instead of FAIL.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:36 +02:00
Michal Simek
8125c980cc microblaze: Fix interrupt handler code
It is better to read ivr and react on it than do long parsing from
two regs. Interrupt controller returs actual irq number.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:34 +02:00
Michal Simek
b26640971a microblaze: Move FSL initialization to board.c
Move FSL out of interrupt controller.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:33 +02:00
Michal Simek
5bbcb6cf22 microblaze: Move timer initialization to board.c
I would like to handle case where system doesn't contain
intc that's why I need timer initialization out of intc code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:31 +02:00
Michal Simek
cc53690e05 microblaze: Fix irq.S code
It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:30 +02:00
Arun Bhanu
398b1d57a6 microblaze: Add FDT support
This patch adds FDT (flattened device tree) support to microblaze arch.

Tested with Linux arch/microblaze kernels with and without compiled in
FDT on Xilinx ML506 board.

Signed-off-by: Arun Bhanu <arun@bhanu.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:13 +02:00
Stefan Roese
2a72e9ed18 ppc4xx: Add option for PPC440SPe ports without old Rev. A support
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 10:27:39 +02:00
Peter Tyser
37e4dafaae nios2: Move cpu/nios2/* to arch/nios2/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
6a8a2b7058 nios: Move cpu/nios/* to arch/nios/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
1e9c26578e sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23]
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
e9a882803e i386: Move cpu/i386/* to arch/i386/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
6260fb0458 microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
8a15c2d10b avr32: Move cpu/at32ap/* to arch/avr32/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
1e3827d9cf mips: Move cpu/mips/* to arch/mips/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
c6fb83d217 blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
a414553485 m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
84ad688473 arm: Move cpu/$CPU to arch/arm/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
8f0fec74ac sh: Move cpu/$CPU to arch/sh/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:17 +02:00
Peter Tyser
8d1f268204 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:16 +02:00
Peter Tyser
819833af39 Move architecture-specific includes to arch/$ARCH/include/asm
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:12 +02:00
Peter Tyser
ea0364f1bb Move lib_$ARCH directories to arch/$ARCH/lib
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk

This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:03 +02:00