This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:
src/soc/intel/fsp_baytrail/chip.h
(git ID da1a70ea from 2016-01-16 as reference).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Andrew Bradford <andrew.bradford@kodakalaris.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
