Most of the memory is being consumed by device binding code,
more space needed for other data structures.
Z-turn board has already hit the limit, others may follow soon.
Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):
root_driver: 108
mod_exp_sw: 108
amba: 120
serial@e0000000 aka uart0: 112
serial@e0001000 aka uart1: 88
spi@e000d000 aka qspi: 120
sdhci@e0100000 aka mmc0: 455
sdhci@e0100000.blk: 208
slcr@f8000000: 96
clkc@100: 72
(total) 1487 = 0x5cf of 0x600
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.
Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.
Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)
Zynq mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch enables CONFIG_REMAKE_ELF for Zynq platform
so that it generates u-boot.elf from binary which works
for all Zynq boards with OF_SEPARATE option enabled.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)
ZynqMP mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bootrom is not capable to work with non aligned bootloader sizes.
SPL with OF_SEPARATE generates non-align images quite often that's
why this change is required before OF_SEPARATE enableding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable ISSI flash for platforms. Xilinx reference boards are also used
internally with different flash part to increase coverage that's why
enable also ISSI parts for all these boards even if that board is
released only with one part.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch enable net configs for zc1275 board.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.
Print the error message unconditionally so the error doesn't go
unnoticed.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patches renames sd nodes in dts to be in line with
kernel. This patch also modifies the references for the same
in code.
It checks mmc first to have no time penalty for new DT node names based
on left-to-right expression evaluation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.
Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d58)
which had nothing to do with MMC power sequence provider.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for nand multi chip select.
Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number
of nand chips.
Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The FSBL copies "Total Partition Word Length" * 4 bytes from the boot.bin,
which implies that the partition size is 4 byte aligned. When writing the
partition, mkimage calculates "Total Partition Word Length" by dividing
the size by 4. This implicitly cuts unaligned bytes at the end of the
added binary.
Instead of rounding down, the size must be round up to 4 bytes and the
binary padded accordingly.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- MIPS: mscc: add support for ServalT SoC family
- MIPS: mscc: add support for Serval SoC family
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAlxIpMwACgkQKPlOlyTy
XBhkLQ//XCrtiY/DYK/BsXINgv61EHqGpXPE63k/hQnelrEIz5ayoqB5UqBp48p4
2XwA/iyP7PEpPeGov/oRGm5aK1wsuz4hl/Graw2XC+VVRkw8g2m/TWpBVN07MCOV
BcePczV4AqPXNomWo3J+oh49vgpw4rQyA/oSrhLRlOBrgz7W2JHvUhANAoIBwsRy
IOxC23wNHDjd+qP7BZIRoT58Zy70xN9JyhXaD823H9J6Szrzj6vKmqd8GNP7G/YP
JmJl4uCWF6RTjfutY+o9Hq6zMWTG8dyDpSusAxlcWwZE4YOK24OTr1uJP8NzfQBU
ShJ4FC6dekkNdmVueSZpL423si6WJCKMW2BMc34vE+pa9iBS8QvNQSRGnL8qjSqu
nkVZWHMZwHd9sVhZMmsfawjhE5EmkFIeYCBuoRcGQmbHkgUjM2CcfdZbzlDlkzKe
xZiitc05pRR2ubHjL76SsJmDCtdieXNkxE6p2Pyfh7blJi4yC84kDndyTrJVZJWi
Ij7jTAKU4VCb77ALv7A6o60WSlBDg619FeomGEr9V4afALd/ww6NbJ36V/fdoVdm
ptnic9pzMLAZjcc53AUR08qXnNq7n96SPMfVo/tp68WkYcy/AV2k7Sg8BE/od1iW
2pbK/WxzOGuo+wZpMDtuqILHDV96wtEtbVIYp9j4xC9j7+LbxSI=
=GjQJ
-----END PGP SIGNATURE-----
Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips
- MIPS: mscc: ocelot: add ethernet switch and network support
- MIPS: mscc: add support for ServalT SoC family
- MIPS: mscc: add support for Serval SoC family
Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add board support, configuration and DTS for Servalt SoC
family. Currently there is one board in this family.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Now that network support is added for the ocelot platform, let's add it
in the default configuration.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In the two commits:
cf3922dddc
mmc: ftsdc010_mci: Sync compatible with DT mmc node
c14e90e844
riscv: dts: Sync DT with Linux Kernel
ftsdc010_mci's compatible has been modified as
"andestech,atfsdc010" for RISC-V synchronization.
But ae3xx.dts and ag101p.dts which are used for
nds32 adp-ae3xx and adp-ag101p platforms did not
be modified correctly at that time. It will cause
mmc detection failure. Fix it here.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Add -mcmodel=large can let elf-mculib have
the same default behavior just like linux-glibc.
And it help to pass U-Boot booting sequence.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
