The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The commit 53b406369e ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
Add a structure which defines the information that is needed for
executing capsule updates on a platform. Some information in the
structure like the dfu string is used for making the update process
more robust while some information like the per platform image GUIDs
is used for fixing issues. Initialise this structure in the board
file, and use the information for the capsule updates.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string
zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init
clk:
- Handle only GATE type clock for Versal
watchdog:
- Update versal driver to handle system reset
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Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.01-rc1
zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string
zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init
clk:
- Handle only GATE type clock for Versal
watchdog:
- Update versal driver to handle system reset
Generate dfu_alt_info setup at runtime for capsule update.
Enabling this feature will help with upgrading boards without remembering
what is where.
The similar change was done for ZynqMP by commit b86f43de0b ("xilinx:
zynqmp: Add support for runtime dfu_alt_info setup").
Code needs to be enabled by CONFIG_SET_DFU_ALT_INFO.
And also enable capsule on disk for RAW firmware images with efidebug
command.
Two indexes are supported for SPL flow. Images can be generated like:
./tools/mkeficapsule --raw spl/boot.bin --index 1 capsule1.bin
./tools/mkeficapsule --raw u-boot.img --index 2 capsule2.bin
Then place them to SD card and load them:
load mmc 0 10000000 capsule1.bin && efidebug capsule update -v 10000000
load mmc 0 10000000 capsule2.bin && efidebug capsule update -v 10000000
FSBL flow will also work where only index 1 capsule is used. There
should be enough space for using boot.bin with bitstream too.
Zynq also support multiple boot locations in SPI or MMC but it is not wired
by this patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/bea5fc75a87a5971f118b46bab4aa7ca39a629c6.1630061610.git.michal.simek@xilinx.com
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.
Add a proper comment to simple_strtoul() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
The system refuses to boot without any environment, so return ENVL_NOWHERE when
there's nowhere to store the environment instead of ENVL_UNKNOWN.
This fixes that the board won't boot from eMMC when CONFIG_ENV_IS_IN_FAT is not
defined, for example. Similar for other combinations.
Fixes: 1025bd098a "xilinx: zynqmp: Add support for saving variables"
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable saving variables to MMC(FAT), NAND, SPI based on primary
bootmode. If bootmode is JTAG, dont save env anywhere(NOWHERE).
Since most of the flashes on zynq evaluation boards are 16MB in size,
set default ENV_OFFSET to 15MB(0xE00000).
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
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Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
Both Zynq and ZynqMP can show silicon versions in SPL boot flow. It is
useful to be aware.
The patch is also fixing possition of these bits on ZynqMP.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
All Xilinx SoCs have repository location filled already but boards are
covered by different fragment which is missing this link.
The patch is extending description with adding proper link to the same
repository.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no need to reference files in common folder back. Simply adding
Makefile to this folder does the job because this "common" location is
already wired in main Makefile.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
zynq-zturn was checked on V5 board, same error.
Maybe Z-turn board have the same problem (board with W25Q128BVFIG).
Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG to enable/disable updating
variables with run time information.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
DEVICE_TREE variable is not exported from dts/Makefile that's why it is
necessary to setup directly before use.
Fixes: 312f2c5b14 ("arm: xilinx: Use device tree which can be passed on cmd line")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The board has two push button connected to MIO pins
50 and 51, which have a pull-down resistor and are
connected to 1.8V when pressed.
These two pins are wrongly initialized with internal
pull-up enabled so they are reported as 1 all the time
with no change when pressed.
Disable the internal pull-up to fix the issue.
Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new jtag distro boot command to look for bootscript
file in DDR and execute it first incase of jtag bootmode.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DEVICE_TREE variable has been added by commit 6ab6b2afa0
("dts: re-write dts/Makefile more simply with Kbuild")
where DT can be specified on command line. If it is not then
CONFIG_DEFAULT_DEVICE_TREE is used to ensure backward compatibility.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no reason to do serial initializationin low level code. Uart
driver does it already based on DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently "script_offset_f" env variable is hardcoded, this variable
specifies from which offset of the flash boot.scr should be read/write.
As flashes are of different sizes having a fixed offset makes it
difficult to load other images into the flash which may overwrite the
boot script or cannot utilize the full memory. This current fix
creates a new config "CONFIG_BOOT_SCRIPT_OFFSET" which holds the
offset address, overwrites the "script_offset_f" variable.
Also removed existing variable with default values, as the default
values are held by CONFIG_BOOT_SCRIPT_OFFSET
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
board_early_init_f added by commit e6cc3b25d7
("arm: zynq: Wire watchdog internals") is no longer needed that's why
remove it also with Kconfig enabling.
Fixes: ccd063e981 ("watchdog: Move watchdog_dev to data section (BSS may not be cleared)")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx Zynq SoC has two sdhci controllers but boot is only possible from
the first one. That's why there is a need to specify controller number.
mmc1 is supposed to be secondary boot device and should be also listed in
distribution boot.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch tries to implement a generic watchdog_reset() function that
can be used by all boards that want to service the watchdog device in
U-Boot. This watchdog servicing is enabled via CONFIG_WATCHDOG.
Without this approach, new boards or platforms needed to implement a
board specific version of this functionality, mostly copy'ing the same
code over and over again into their board or platforms code base.
With this new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).
This patch also adds a new flag to the GD flags, to flag that the
watchdog is ready to use and adds the pointer to the watchdog device
to the GD. This enables us to remove the global "watchdog_dev"
variable, which was prone to cause problems because of its potentially
very early use in watchdog_reset(), even before the BSS is cleared.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Maxim Sloyko <maxims@google.com>
Cc: Erik van Luijk <evanluijk@interact.nl>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: "Álvaro Fernández Rojas" <noltari@gmail.com>
Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
This patch checks for zynq aes & rsa commands max parameters count. Also
checks minimum number of parameters count for aes command.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Update boot_targets based on bootmode to run corresponding
distroboot command first.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq and ZynqMP are sharing similar code and there is no reason to do
code duplication. Move zynq_board_read_rom_ethaddr() to common file for
easier conversion to DM.
Use ZynqMP version that's why also add CONFIG_ZYNQ_EEPROM_BUS to Syzygy
which is only one Zynq board which is using this feature.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
If SYS_LONGHELP is disabled the following warning is generated:
board/xilinx/zynq/cmds.c:496:13: warning: ‘zynq_help_text’ defined but
not used [-Wunused-variable]
Normal way for fixing this is to guard the whole variable.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
