2 commits

Author	SHA1	Message	Date
Dave Liu	c360ceac02	fsl-ddr: add the DDR3 SPD infrastructure ... - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>	2009-03-30 13:33:50 -05:00
Haiying Wang	dfb49108e4	Pass dimm parameters to populate populate controller options ... Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>	2008-10-18 21:54:04 +02:00

Renamed from cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h (Browse further)