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33364 commits

Author SHA1 Message Date
Anton Vorontsov
fd6646c0b9 mpc83xx: Add support for MPC83xx PCI-E controllers
This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.

The patch is based on Tony Li and Dave Liu work[1].

Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.

To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.

[1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html

Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Ira Snyder
88ecf55cab MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent mode
When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do
not enable them. See the MPC8349EA Reference Manual, Section 4.4.2
"Clocking in PCI Agent Mode".

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Ira Snyder
75f35209f7 83xx: PCI agent mode fixes for multi-board systems
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode,
the boards will lock up the PCI bus by scanning against each other.

The boards lock against each other by trying to access the PCI bus before
clearing their configuration lock bit. Both boards end up in a loop,
sending and receiving "Target Not Ready" messages forever.

When running in PCI agent mode, the scanning now takes place after the
boards have cleared their configuration lock bit.

Also, add a missing declaration to the mpc83xx.h header file, fixing a
build warning.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Ron Madrid
455a46915b mpc83xx: Size optimization of start.S
Currently there are in excess of 100 bytes located at the beginning of the image
built by start.S that are not being utilized.  This patch moves a few functions
into this part of the image.  This will create a greater number of *available*
bytes that can be used by board specific code in NAND builds and will decrease
the size of the assembled code in other builds.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Kim Phillips
be4880ebe4 Merge branch 'master' into next 2009-01-21 18:38:51 -06:00
Wolfgang Denk
72d15e705b Prepare v2009.01
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-21 23:08:12 +01:00
Wolfgang Denk
635e5f8fc8 Prepare 2009.01-rc3
Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-18 21:37:48 +01:00
Wolfgang Denk
65ff996802 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-01-18 21:11:05 +01:00
Mike Frysinger
4cda437898 build system: treat all Darwin's alike
The x86 based version of Darwin behaves the same quirky way as the powerpc
Darwin, so only check HOSTOS when setting up Darwin workarounds.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-18 21:08:45 +01:00
Peter Korsgaard
c088a108c7 fdt_resize(): fix actualsize calculations with unaligned blobs
The code in fdt_resize() to extend the fdt size to end on a page boundary
is wrong for fdt's not located at an address aligned on a page boundary.
What's even worse, the code would make actualsize shrink rather than grow
if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
causing fdt_add_mem_rsv to fail.

Fix it by aligning end address (blob + size) to a page boundary instead.
For aligned fdt's this is equivalent to what we had before.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2009-01-17 13:03:29 -05:00
Mike Frysinger
fadad1573f ncb: use socklen_t
The recvfrom() function takes a socklen_t, not an int.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-16 09:31:05 +01:00
Wolfgang Denk
71771e501c Merge branch 'master' of git://git.denx.de/u-boot-sh 2009-01-16 09:22:25 +01:00
Wolfgang Denk
e62dea46aa Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-01-16 09:17:53 +01:00
Jean-Christophe PLAGNIOL-VILLARD
fc83c9273c sh: serial: use readx/writex accessors
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 11:59:20 +09:00
Jean-Christophe PLAGNIOL-VILLARD
9e1fa628bd sh: serial: coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 11:03:17 +09:00
Nobuhiro Iwamatsu
c9935c9925 sh: Fix compile error on lowlevel_init file
lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:27 +09:00
Kieran Bingham
a5b04d00bf sh: Fix up rsk7203 target for out of tree build
Fix up rsk7203 target to build successfully using out-of-tree build.

Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:27 +09:00
Jean-Christophe PLAGNIOL-VILLARD
f7e78f3b74 sh: use write{8,16,32} in all lowlevel_init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:27 +09:00
Jean-Christophe PLAGNIOL-VILLARD
e443077962 sh: lowlevel_init coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:26 +09:00
Jean-Christophe PLAGNIOL-VILLARD
85cb052ee4 sh: update sh2/sh2a timer coding style
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:26 +09:00
Jean-Christophe PLAGNIOL-VILLARD
1e15ff9993 sh: update sh timer coding style
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:26 +09:00
Wolfgang Denk
0e3ece3380 Prepare 2009.01-rc2
Update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-14 23:26:05 +01:00
Wolfgang Denk
e92c9a860e cpu/mpc824x/Makefile: fix warning with parallel builds
Parallel builds would occasionally issue this build warning:

    ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists

Use "ln -sf" as quick work around for the issue.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-14 22:35:30 +01:00
Matthias Fuchs
3ba605d4be ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards
This patch adds esd's loadpci BSP command to CPCI4052 and
CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14 11:20:07 +01:00
Matthias Fuchs
600fe46fb3 ppc4xx: Disable pci node in device tree on CPCI405 pci adapters
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14 11:18:53 +01:00
Matthias Fuchs
f6a1f490d2 ppc4xx: Cleanup CPCI405 board code
This patch cleans up CPCI405 board support:
- wrap long lines
- unification of spaces in function calls
- remove dead code

Use correct io accessors on peripherals.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14 11:18:20 +01:00
Matthias Fuchs
fceebb45a0 ppc4xx: Enable auto RS485 mode on PLU405 boards
This patch turns on the auto RS485 mode in the 2nd external
uart on PLU405 boards. This is a special mode of the used
Exar XR16C2850 uart. Because these boards only have a 485 physical
layer connected it's a good idea to turn it on by default.

Signed-off-by: Matthias Fuchs <mf@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14 11:17:52 +01:00
Wolfgang Denk
5f01ea63a6 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-01-14 00:27:06 +01:00
Wolfgang Denk
bae6d5e412 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-01-14 00:26:48 +01:00
Haiying Wang
b5f65dfa9a Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:58:46 -06:00
Haiying Wang
950264317e Change DDR tlb start entry to CONFIG param for 85xx
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:47:07 -06:00
Roy Zang
6d3a10f73e Change PCIE1&2 deciide logic on MPC8544DS board more readable
The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13 16:32:53 -06:00
Roy Zang
028e116811 PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13 16:32:52 -06:00
Roy Zang
9afc2ef030 Fix IO port selection issue on MPC8544DS and MPC8572DS boards
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13 16:32:52 -06:00
Becky Bruce
3e3fffe3ba mpc8610hpcd: Fix PCI mapping concepts
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-01-13 15:27:46 -06:00
Becky Bruce
79e436cad3 sbc8641d: Fix PCI mapping concepts
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-01-13 15:27:45 -06:00
Wolfgang Denk
a9f3acbcd0 MPC86xx: fix build warnings
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-12 14:50:35 +01:00
Wolfgang Denk
950309c643 Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2009-01-10 18:18:37 +01:00
Mike Frysinger
032a1c934e bf537-stamp/nand: fix board_nand_init prototype
The board_nand_init() function should return an int, not void.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07 03:00:22 -05:00
Mike Frysinger
687f952e41 Blackfin: drop CONFIG_SPI handling in board init
The eeprom SPI init functions are duplicated as the common code already
executes these for us.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07 03:00:06 -05:00
Mike Frysinger
e7e684b10d Blackfin: fix out-of-tree building with ldscripts
Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07 02:59:50 -05:00
Mike Frysinger
b9eecc342f Blackfin: fix linker scripts to work with --gc-sections
Make sure all .text sections get pulled in and the entry point is properly
referenced so they don't get discarded when linking with --gc-sections.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07 02:59:46 -05:00
Mike Frysinger
509fc553bc Blackfin: set proper LDRFLAGS for parallel booting LDRs
In order to boot an LDR out of parallel flash, the ldr utility needs a few
flags to tell it to generate the right header.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07 02:59:05 -05:00
Jean-Christophe PLAGNIOL-VILLARD
3dd9395a0d at91rm9200: move define from lowlevel_init to header
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:41:59 +01:00
Jean-Christophe PLAGNIOL-VILLARD
8a48686fac m501sk: move to the common memory setup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:38:01 +01:00
Jean-Christophe PLAGNIOL-VILLARD
d481c80d78 at91rm9200: rename lowlevel init value to CONFIG_SYS_
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:37:39 +01:00
Nicolas Ferre
4e170b1662 at91: add at91sam9xeek board support
At91sam9xe is basically an at91sam9260 with embedded flash. We can manage
it as another entry for at91sam9260 in the Makefile.

Check documentation at :
http://www.atmel.com/dyn/products/product_card.asp?part_id=4263

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:37:19 +01:00
Jean-Christophe PLAGNIOL-VILLARD
9ffd53db87 fix bmp_logo.h make dependencies to allow parallel build
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:37:04 +01:00
Jean-Christophe PLAGNIOL-VILLARD
e12d9a8fb4 at91: Fix Atmel's at91sam9 boards out of tree build
introduced in commit 89a7a87f08

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:11:52 +01:00
Wolfgang Denk
f85cd46918 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-12-30 23:30:47 +01:00