Commit graph

15 commits

Author SHA1 Message Date
Lokesh Vutla
ee3c6532be ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00
Lokesh Vutla
8b01ebd812 ARM: keystone2: PLL: Enable glitch free initialization sequence
Update the PLL initialization sequence to avoid glitches while
programming. User guide for the same is available at[1].

[1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13 15:54:36 -05:00
Masahiro Yamada
43ebbfc39f ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()
The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.

Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-08 09:33:13 -04:00
Lokesh Vutla
ef76ebb1ef ARM: keystone2: K2G: Add support for different arm/device speeds
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:44 -04:00
Lokesh Vutla
5cd1f6bd7a ARM: keystone2: Allow for board specific speed definitions
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:43 -04:00
Vitaly Andrianov
e6d71e1ca5 ARM: k2g: Add clock information
Add clock information for Galileo

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:22:16 -04:00
Vitaly Andrianov
bda920c65e ARM: k2g: Add pll data
Add pll data for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:15 -04:00
Lokesh Vutla
8626cb8021 ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-17 20:16:13 -04:00
Lokesh Vutla
fe772ebd28 ARM: keystone2: Use common definition for clk_get_rate
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:55 -04:00
Lokesh Vutla
94069301ba ARM: keystone2: Cleanup init_pll definition
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:53 -04:00
Lokesh Vutla
74af583e9f ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:53 -04:00
Lokesh Vutla
7b50e1599f ARM: keystone2: Fix dev and arm speed detection
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:52 -04:00
Lokesh Vutla
c321a23624 ARM: keystone2: Cleanup PLL init code
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:52 -04:00
Vitaly Andrianov
437a7293a7 keystone2: use correct EFUSE_BOOTROM fileds to configure speed
The get_max_arm_speed() and get_max_dev_speed() used wrong register
fields to get the maximum speeds. This commit fixes the bug.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-19 16:46:46 -04:00
Masahiro Yamada
39a723452f ARM: keystone: move SoC sources to mach-keystone
Move
arch/arm/cpu/armv7/keystone/* -> arch/arm/mach-keystone/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2015-02-21 08:23:52 -05:00
Renamed from arch/arm/cpu/armv7/keystone/clock.c (Browse further)