Commit graph

86738 commits

Author SHA1 Message Date
FUKAUMI Naoki
afb4f55565 arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-order
use common one defined in rk356x-u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
74f162a1ea arm: dts: rk356x: Makefile: sort
sort alphanumerically.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
e62ba9016e doc: rockchip: update list of Radxa ROCK (Pi) 4 boards
add Radxa ROCK (Pi) 4 variants.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
1495bf17b8 configs: rockchip: add Radxa ROCK 4C+
add defconfig for Radxa ROCK 4C+.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
71a95e2efd arm: dts: rockchip: add Radxa ROCK 4C+
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+

Add support for Radxa ROCK 4C+ SBC.

Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec

Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.

Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
5488a5b1db configs: rockchip: rock-pi-4: use dtb for ROCK Pi 4A instead of 4B
rk3399-rock-pi-4a.dtb is enough for Radxa ROCK Pi 4A/B/A+/B+ and ROCK 4SE.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
d0e62eeda8 arm: dts: rockchip: rock-pi-4: sync with Linux 6.3
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.

because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 20:30:12 +08:00
Tianling Shen
7000a60947 rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.

The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:58:25 +08:00
Eugen Hristev
4a08ca6192 reset: reset-rockchip: fix trivial line spacing alignment
Fix line spacing aligment in bind function

Fixes: 760188c1aa ("rockchip: reset: support a (common) rockchip reset drivers")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:56:16 +08:00
Eugen Hristev
30850b6919 clk: rockchip: correct trivial typo in debug message
s/faile/failed in debug message

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:28:44 +08:00
Eugen Hristev
e04b67a7f4 pci: pcie_dw_rockchip: release resources on failing probe
Implement a resource release mechanism on failing probe.
Without this, a strange situation can happen e.g. when init port fails,
or attempting to get the PHY fails, because the gpios have been
requested first, and if the user tries to do 'pci enum' again, the
driver will fail with 'can't find reset gpios' even if the gpios are
there, just because they were blocked by a previous probe attempt.
It is only natural to release the acquired resources if the probe fails,
just for consistency if nothing else.
This way on subsequent probe attempts, the user will get the same error
message, and not something different that doesn't make sense.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:26:59 +08:00
Tom Rini
f1d33a44ca Prepare v2023.07-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-08 14:16:32 -04:00
Tom Rini
56a3a499f4 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-08 13:43:35 -04:00
Judith Mendez
8774e45e89 board: ti: am64x: Add support for AM64B SK
The AM64x SR2.0 SK board uses "AM64B-SKEVM" as the EEPROM identifier.
This board is similar to the AM64x SKEVM except that it has a new
PMIC that will be enabled in the future and consequently could use a
different device tree file in the future.

For now we treat the board same as an AM64x SK.

Signed-off-by: Judith Mendez <jm@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08 09:27:20 -04:00
Nikhil M Jain
7a17e4c6f1 common: spl: spl: Remove video driver before u-boot proper
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08 09:26:12 -04:00
Nikhil M Jain
72236302e6 board: ti: am62x: evm: Add necessary functions to call splash screen
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table,
enable cache to allow copying of bmp image to frame buffer and display
it using splash_display.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08 09:26:12 -04:00
Nikhil M Jain
852480c1f4 board: ti: am62x: am62x: Change splashimage and splashsource
Change splashimage which is bmp image loadaddr to 0x80200000 since stack
is situated at 0x80477660 as splash framework requires bmp image to be
present above stack.

Change splashsource to sf to support loading bmp image from ospi flash
memory.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08 09:26:12 -04:00
Nikhil M Jain
5c64598bf7 configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screen
To enable splash at A53 SPL, need to do memory map changes which
involves locate stack above malloc and have enough space to load bmp
image above stack. To load a 1920X1200 image a minimum of 8.8MB space is
needed, to support it move malloc down to 0x80b80000 from 0x80480000 and
bss to 0x80c80000 to have 1MB buffer between malloc and BSS.

Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB.
Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set
to 2KB.
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc
and reports for stack overflow.

Memory map at A53 SPL before splash screen
0x80000000+---------------------+
          |    Empty 512 KB     |
          |                     |
0x80080000+---------------------+
          |     Text Base       |
          |       352 KB        |
          |                     |
0x800D8000+---------------------+
          |                     |
          |                     |
          |    Empty 3.6MB      |
          |                     |
          |                     |
0x80477660+---------------------+
          |    Stack 2 KB       |
0x80477e60+---------------------+
          |     GD 416 Bytes    |
0x80478000+---------------------+
          |    Malloc 352 KB    |
          |                     |
0x80480000+---------------------+
          |                     |
          |                     |
          |                     |
          |                     |
          |   Empty 5.5 MB      |
          |                     |
          |                     |
          |                     |
          |                     |
0x80a00000+---------------------+
          |                     |
          |      BSS 512 KB     |
          |                     |
0x80a80000+---------------------+
          |                     |
          |                     |
          |                     |
          |                     |
          |   Empty 5.5 MB      |
          |                     |
          |                     |
          |                     |
          |                     |
0x81000000+---------------------+FIT Image load address

New memory map with splash screen at SPL
0x80000000+---------------------+
          |    Empty 512 KB     |
          |                     |
0x80080000+---------------------+
          |     Text Base       |
          |       352 KB        |
          |                     |
0x800D8000+---------------------+
          |    Empty 1.1MB      |
          |                     |
0x80200000+---------------------+
          |                     |
          |                     |
          |                     |
          |   BMP Image Load    |
          |                     |
          |       9.4 MB        |
          |                     |
          |                     |
          |                     |
          |                     |
          |                     |
          |                     |
0x80b77660+---------------------+
          |     Stack 2KB       |
0x80b77e60+---------------------+
          |    GD 416 Bytes     |
0x80b78000+---------------------+
          |                     |
          |    Malloc 352KB     |
0x80b80000+---------------------+
          |                     |
          |     Empty 1 MB      |
          |                     |
0x80c80000+---------------------+
          |     BSS 512 KB      |
          |                     |
0x80d00000+---------------------+
          |                     |
          |                     |
          |    Empty 3.0 MB     |
          |                     |
          |                     |
          |                     |
0x81000000+---------------------+FIT Image load addressi

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08 09:26:12 -04:00
Dominique Martinet
b1d3013d02 btrfs: fix offset when reading compressed extents
btrfs_read_extent_reg correctly computed the extent offset in the
BTRFS_COMPRESS_NONE case, but did not account for the 'offset - key.offset'
part correctly in the compressed case, making the function read
incorrect data.

In the case I examined, the last 4k of a file was corrupted and
contained data from a few blocks prior, e.g. reading a 10k file with a
single extent:
btrfs_file_read()
 -> btrfs_read_extent_reg
    (aligned part loop, until 8k)
 -> read_and_truncate_page
   -> btrfs_read_extent_reg
      (re-reads the last extent from 8k to the end,
      incorrectly reading the first 2k of data)

This can be reproduced as follow:
$ truncate -s 200M btr
$ mount btr -o compress /mnt
$ pat() { dd if=/dev/zero bs=1M count=$1 iflag=count_bytes status=none | tr '\0' "\\$2"; }
$ { pat 4K 1; pat 4K 2; pat 2K 3; }  > /mnt/file
$ sync
$ filefrag -v /mnt/file
File size of /mnt/file is 10240 (3 blocks of 4096 bytes)
 ext:     logical_offset:        physical_offset: length:   expected: flags:
   0:        0..       2:       3328..      3330:      3:             last,encoded,eof
$ umount /mnt

Then in u-boot:
=> load scsi 0 2000000 file
10240 bytes read in 3 ms (3.3 MiB/s)
=> md 2001ff0
02001ff0: 02020202 02020202 02020202 02020202  ................
02002000: 01010101 01010101 01010101 01010101  ................
02002010: 01010101 01010101 01010101 01010101  ................

(02002000 onwards should contain '03' pattern but went back to 01,
start of the extent)

After patch, data is read properly:
=> md 2001ff0
02001ff0: 02020202 02020202 02020202 02020202  ................
02002000: 03030303 03030303 03030303 03030303  ................
02002010: 03030303 03030303 03030303 03030303  ................

Note that the code previously (before commit e3427184f3 ("fs: btrfs:
Implement btrfs_file_read()")) did not split that read in two, so
this is a regression even if the previous code might not have been
handling offsets correctly either (something that booted now fails to
boot)

Fixes: a26a6bedaf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()")
Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Qu Wenruo <wqu@suse.com>
2023-05-08 09:23:53 -04:00
Tom Rini
fbfe7fb5ae Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- cmd: tlv_eeprom: Misc cleanups & improvements (Josua)
2023-05-08 09:10:39 -04:00
Josua Mayer
fa0af90a0e cmd: tlv_eeprom: enable 'dev' subcommand before 'read'
Move the handler for "tlv_eeprom dev X" command to the beginning of
do_tlv_eeprom, to allow using it before issuing a "read" command for
currently selected eeprom.

Also remove the check if eeprom exists, since that can only work after
the first execution of read_eeprom triggered device lookup.
Instead accept values up to the defined array size (MAX_TLV_DEVICES).

Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-05-08 10:47:13 +02:00
Josua Mayer
f6eff35b8c cmd: tlv_eeprom: handle -ENODEV error from read_eeprom function
When tlv eeprom does not exist, return error code instead of quietly
making up tlv structure in memory.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-05-08 10:47:11 +02:00
Josua Mayer
425d963dac cmd: tlv_eeprom: remove use of global variable has_been_read
has_been_read is only used as an optimization for do_tlv_eeprom.
Explicitly use and set inside this function, thus making read_eeprom
stateless.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-05-08 10:47:08 +02:00
Josua Mayer
dfda0c0140 cmd: tlv_eeprom: remove use of global variable current_dev
Make tlv_eeprom command device selection an explicit parameter of all
function calls.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-05-08 10:47:05 +02:00
Tom Rini
1917a1a8a8 Merge branch 'for-2023.07-2' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds misc fixes for cssi boards and activates
CPM relocation in order to enable the use of SCC4 in
QMC (QUICC Multi-Channel) mode.
2023-05-07 09:44:27 -04:00
Tom Rini
ae0772f333 Merge branch '2023-05-05-networking-updates'
- Cleanup NFS support, add NFSv1 support, assorted IPv6 improvements,
  PHY cleanups and improvements, ksz9477, ldpaa and rtl8169
  improvements, overall network performance improvements.
2023-05-06 10:34:34 -04:00
Chris Morgan
6cf6fe2537 board: rockchip: add Anbernic RGXX3 Series Devices
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:

 - Anbernic RG353M
 - Anbernic RG353P
 - Anbernic RG353V
 - Anbernic RG353VS
 - Anbernic RG503

The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.

Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.

The common specifications for each device are:

 - Rockchip RK3566 SoC
 - 2 external SDMMC slots
 - 1 USB-C host port, 1 USB-C peripheral port
 - 1 mini-HDMI output
 - MIPI-DSI based display panel
 - ADC controlled joysticks with a GPIO mux
 - GPIO buttons
 - A PWM controlled vibrator
 - An ADC controlled button

All of the common features are defined in the devicetree synced from
upstream Linux.

TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:45:05 +08:00
Christian Kohlschütter
c2d5edff91 rk3399: r4s: Derive local MAC address if EEPROM is missing
Some RK3399 boards, such as newer revisions of NanoPi R4S, do not
provide an EEPROM chip containing a globally unique MAC address.

Currently, this means that a randomly generated temporary MAC address
may be generated each time the device is rebooted, leading to ARP cache
issues and other confusing bugs.

Since RK3399 CPUs provide a built-in unique serial number, we can
reliably derive a locally MAC address from it by reading the
corresponding bits from the non-secure efuse block.

Enable configuration options that allow deriving a local MAC address
from the CPU serial number.
2023-05-06 17:28:18 +08:00
Johan Jonker
53c5093b2e include: fdtdec: decouple fdt_addr_t and phys_addr_t size
The DT specification supports CPUs with both 32-bit and 64-bit addressing
capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled
by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions
with a 64-bit reg property. These partitions synced from Linux end up with
the wrong offset and sizes when only the lower 32-bit is passed.
Decouple the fdt_addr_t and phys_addr_t size as they don't necessary
match.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:28:18 +08:00
Johan Jonker
55cd74d691 arm: stm32mp: spl: fix function with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
84404d8165 drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
0d01046ea3 drivers: use devfdt_get_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
320a1938b6 drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
842fb5de42 drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
a12a73b664 drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
e5822ecba2 drivers: use dev_read_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
8fa64bd171 spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes. As we are there also streamline the error
response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-06 17:28:18 +08:00
Johan Jonker
b526656c5b core: read: add dev_read_addr_index_ptr function
Add dev_read_addr_index_ptr function with the
same functionality as dev_read_addr_index,
but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for dev_read_addr_ptr() function.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
aa4f61a776 core: fdtaddr: add devfdt_get_addr_size_index_ptr function
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.

Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
66a1d38c98 rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
The Rockchip SoC rk3288 has 2 types of device trees floating around.
A 64bit reg size when synced from Linux and a 32bit for U-boot.
A pre-probe function in the syscon class driver assumes only 32bit.
For other odd reg structures the regmap must be defined in the individual
syscon driver. Store rk3288 platdata in a regmap before pre-probe
during bind.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
0fbb96964b core: remap: fix regmap_init_mem_plat() reg size handeling
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
aecae81a35 include: dm: ofnode: fix headers
When fdt_addr_t and phys_addr_t are split it turns out that
the header don't match the functions, so fix the headers.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:28:18 +08:00
Johan Jonker
3eac1db2df rockchip: spi: rk_spi: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_spi.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
88a9e58b99 rockchip: pwm: rk_pwm: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_pwm.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
e9eddb75c5 rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
ac9198d1d5 rockchip: adc: rockchip-saradc: use dev_read_addr_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:28:18 +08:00
Johan Jonker
bdf57198ba mtd: nand: add support for the Sandisk SDTNQGAMA chip
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-06 17:28:17 +08:00
Johan Jonker
df08f74774 mtd: nand: raw: rockchip_nfc: fix oobfree offset and description
The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 positions before
ECC. Update the description for U-boot.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:28:17 +08:00
Johan Jonker
14eb61aa25 mtd: nand: raw: rockchip_nfc: add flash_node to chip structure
Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-06 17:28:17 +08:00
Johan Jonker
1b3fcb3c04 mtd: nand: raw: rockchip_nfc: add layout structure
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-06 17:28:17 +08:00