Commit graph

6 commits

Author SHA1 Message Date
Prabhakar Kushwaha
fbe76ae4e3 board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.

So, use CONFIG_SPL_NAND_BOOT config.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-02 14:10:13 -08:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Prabhakar Kushwaha
f64bd7c038 powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:47 -05:00
Priyanka Jain
765b0bdb89 board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Prabhakar Kushwaha
f159326926 board/bsc9131rdb:Add NAND boot support using new SPL format
- Add NAND boot target
   - defines constants
   - Add spl_minimal.c to initialise DDR
   - update TLB entries as per NAND boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:07 -05:00
Prabhakar Kushwaha
7530d341c7 powerpc/mpc85xx:Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
 is an integrated device that targets Femto base station market. It combines
 Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
 MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
   -----------------
     -1Gbyte DDR3 (on board DDR)
     -128Mbyte 2K page size NAND Flash
     -256 Kbit M24256 I2C EEPROM
     -128 Mbit SPI Flash memory
     -USB-ULPI
     -eTSEC1: Connected to RGMII PHY
     -eTSEC2: Connected to RGMII PHY
     -DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:29 -05:00