Commit graph

38891 commits

Author SHA1 Message Date
Kever Yang
d26f375ae4 ARM64: evb-rk3399: add a README for this board setup
Add a README to guide people flash the ATF and U-Boot
with Rockchip tools to bring up to board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:46 -06:00
Kever Yang
7e24349698 config: add config file for evb-rk3399
This patch add basic config option for evb-rk3399 board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:46 -06:00
Kever Yang
a381bcf529 ARM64: rockchip: add support for rk3399 SoC based evb
RK3399 is a SoC from Rockchip with dual-core Cortex-A72
and quad-core Cortex-A53 CPU. It supports two USB3.0
type-C ports and two USB2.0 EHCI ports. Other interfaces
are very much like RK3288, the DRAM are 32bit width address
and support address from 0 to 4GB-128MB range.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00
Kever Yang
777c834fd4 dts: add support for Rockchip rk3399 soc
These files are from kernel upstream:
"649a371 Add linux-next specific files for 20160616"
with some modification need by U-Boot:
- chosen with stdout-path to uart2.
- add clock-frequency for uart2

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00
Xu Ziyuan
a16e2e0680 rockchip: update fastboot usage
Introduce how to use fastboot feature on rk3288.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00
Kever Yang
9191090e34 mkimage: rockchip: add suport for rk33 serial
Add support for rockchip rk33 series Soc like rk3368 and rk3399

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00
Simon Glass
c3aad6f65b rockchip: Use rockchip_get_clk() to obtain the SoC clock
The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.

Fix this by calling rockchip_get_clk() instead.

Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2016-07-25 20:46:45 -06:00
Simon Glass
a617c5d3e2 rockchip: Add a way to obtain the main clock device
On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a function
to obtain the core clock.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00
Simon Glass
c57f806bf2 dm: core: Add a way to find a device by its driver
Some SoCs have a single clock device. Provide a way to find it given its
driver name. This is handled by the linker so will fail if the name is not
found, avoiding strange errors when names change and do not match. It is
also faster than a string comparison.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:43 -06:00
Heiko Stübner
c3f03ffbe3 rockchip: rk3288: fix FREF_MIN_HZ constant
According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Heiko Stübner
b339b5dbca cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Heiko Stübner
041cdb5f3d cosmetic: rockchip: sort socs according to numbers
Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Heiko Stübner
23c3042b10 cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Heiko Stübner
9f862ec717 cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
The rk3288 pinctrl is very specific to this soc, so should
not hog the generic rockchip naming.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Xu Ziyuan
266c8fad51 rockchip: rk3288: add fastboot support
Enable fastboot feature on rk3288.

This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Xu Ziyuan
9424f14183 usb: dwc2 : invalidate dcache before starting DMA
Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt the buffer in memory while the DMA
is still going on. Cache-line replacement can happen if the CPU tries to
bring some other memory locations into the cache while the DMA is going
on.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Xu Ziyuan
4711788267 usb: dwc2-otg: adjust fifo size via platform data
The total FIFO size of some SoCs may be different from the existen, this
patch supports fifo size setting from platform data.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Xu Ziyuan
fab3357916 usb: rockchip-phy: implement USB2.0 phy control
So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
Innosilicon. This patch applys dwc2 usb driver framework to implement
phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Andreas Färber
ad8fe6b964 rockchip: Exclude rk_timer for ARM64
It conflicts with the generic_timer.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Kever Yang
5f30bf764b mkimage: rockchip: add suport for rk33 serial
Add support for rockchip rk33 series Soc like rk3368 and rk3399

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Andreas Färber
e0f5dbcb4b rockchip: Clean up CPU selection
In preparation for RK3368 and RK3399, which need to select ARM64, don't
select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:19 -06:00
Kever Yang
c418addfa9 board: move all the rockchip board in one folder
The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them
to 'rockchip' which is a real _vendor_ name, and meet the architecure
'board/<vendor>/<board-name>/'.

More boards from rockchip like evb_rk3288, evb_rk3399 will comes later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
2016-07-25 20:44:19 -06:00
Xu Ziyuan
744368d6ae rockchip: add basic support for evb-rk3288 board
evb-3288 board RK3288-based development board with 2 USB ports, HDMI,
VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes
on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to
display pins, I2C, SPI, UART and GPIOs. This add some basic files
required to allow the board to output serial messaged and can run
command(mmc info etc).

evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:18 -06:00
Xu Ziyuan
b47ea79219 rockchip: add option to change method of loading u-boot
If we would like to boot from SD card, we have to implement mmc driver
in SPL stage, and get a slightly large SPL binary. Rockchip SoC's
bootrom code has the ability to load spl and u-boot, then boot.

If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to
bootrom in board_init_f(), then bootrom loads u-boot binary.

Loading sequence after rework:
bootrom ==> spl ==> bootrom ==> u-boot

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:18 -06:00
Tom Rini
4579720412 Prepare v2016.09-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25 22:25:52 -04:00
Tom Rini
6a056c442f sandbox: Migrate CONFIG_I2C_EEPROM
Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago,
but sandbox was skipped.  Leave it off for sandbox_spl where it does not
build, but does not need to be either.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25 18:18:15 -04:00
Alexey Brodkin
d7b60fbfa6 splash: Accommodate DM_USB in splash_init_usb()
Current implementation of splash_init_usb() requires usb_stor_scan()
which doesn't exist in case of DM_USB simply because real probing
happens right in usb_init().

So disable usage of usb_stor_scan() in case of DM_USB.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Robert Winkler <robert.winkler@boundarydevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-25 22:42:10 +02:00
Scott Wood
b60038ccab powerpc/86xx: Pass -mcpu=7400 to GCC
Without this, GCC uses the toolchain default, which may be incompatible
with -maltivec.

Signed-off-by: Scott Wood <oss@buserror.net>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-25 12:51:16 -07:00
Tom Rini
fd42e1b589 Merge git://git.denx.de/u-boot-nand-flash 2016-07-25 14:49:54 -04:00
Masahiro Yamada
e312e745db arm64: thunderx_88xx_defconfig: remove unneeded CONFIG_SYS_EXTRA_OPTIONS
ARM64 is correctly select'ed in arch/arm/Kconfig, so this line in
the defconfig is unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:56 -04:00
Simon Glass
d6a33918fb dtoc: Correct the type widening code in fdt_fallback
This code does not match the fdt version in fdt.py. When dtoc is unable to
use the Python libfdt library, it uses the fallback version, which does not
widen arrays correctly.

Fix this to avoid a warning 'excess elements in array initialize' in
dt-platdata.c which happens on some platforms.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:55 -04:00
Simon Glass
c55d02b2ac hashtable: Fix compiler warning on 32-bit sandbox
This fixes a mismatch between the %zu format and the type used on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:55 -04:00
Simon Glass
5afb8d151f part_efi: Fix compiler warning on 32-bit sandbox
This fixes a mismatch between the %zu format and the type used on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:54 -04:00
Simon Glass
1bb718cdab lzmadec: Use the same type as the lzma call
With sandbox on 32-bit the size_t type can be a little inconsistent. Use
the same type as the caller expects to avoid a compiler warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:54 -04:00
Simon Glass
5923c843ba sandbox: Add instructions about building on 32-bit machines
Sandbox is built with 64-bit ints by default. This doesn't work properly on
32-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:05:53 -04:00
mario.six@gdsys.cc
713fb2dcb2 tools, rsa: Further minor cleanups on top of c236ebd and 2b9ec7
[NOTE: I took v1 of these patches in, and then v2 came out, this commit
is squashing the minor deltas from v1 -> v2 of updates to c236ebd and
2b9ec76 into this commit - trini]

- Added an additional NULL check, as suggested by Simon Glass to
  fit_image_process_sig
- Re-formatted the comment blocks

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
[For merging the chnages from v2 back onto v1]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:01:36 -04:00
Russ Dill
335b4e53c9 ARM: am33xx: Always inhibit init/refresh during DDR phy init
A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:

69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"

The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.

Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:00:06 -04:00
Russ Dill
3325b06556 ARM: am33xx: Fix DDR init delay placement
The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.

Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:00:06 -04:00
Alexander Graf
492716662f efi_loader: Make exposed image loader path absolute
When loading an efi image, we pass it the location it was loaded from.

On file system backends, there are no relative paths, so we should always
pass in absolute ones. For network paths, we may be relative.

This fixes distro booting with grub2 for me when it fetches the grub2 config
file from the loader partition.

Reported-by: york sun <york.sun@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-07-25 12:00:06 -04:00
mario.six@gdsys.cc
e8fb4358c2 common: fit: Allow U-Boot images to be booted
In certain circumstances it comes in handy to be able to boot into a second
U-Boot. But as of now it is not possible to boot a U-Boot binary that is inside
a FIT image, which is problematic for projects that e.g. need to guarantee a
unbroken chain of trust from SOC all the way into the OS, since the FIT signing
mechanism cannot be used.

This patch adds the capability to load such FIT images.

An example .its snippet (utilizing signature verification) might look
like the following:

images {
	firmware@1 {
		description = "2nd stage U-Boot image";
		data = /incbin/("u-boot-dtb.img.gz");
		type = "firmware";
		arch = "arm";
		os = "u-boot";
		compression = "gzip";
		load = <0x8FFFC0>;
		entry = <0x900000>;
		signature@1 {
			algo = "sha256,rsa4096";
			key-name-hint = "key";
		};
	};
};

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:00:05 -04:00
Karicheri, Muralidharan
bcdc1c8376 keystone: k2h/e/l: Fix DMA coherency for QM PDSP
commit 1f807a9f32 ("ARM: keystone2: Refactor MSMC macros to avoid
left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid.
This, in effect disabled DMA coherency for QM PDSP.

Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs,
the #ifdef should been removed in the first place. Do the same.

Fixes: 1f807a9f32 ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery")
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:00:05 -04:00
mario.six@gdsys.cc
c4974632e2 cmd: misc: Add support for fractions in sleep
A feasible way to communicate certain errors for devices that have no
other way of signalling besides LEDs is to flash these LEDs. For errors
in U-Boot, a script that utilizes the led and sleep commands would be a
practicable way, but currently the sleep command can only delay for an
integral amount of seconds, which is too slow to create an easily
noticeable pattern for flashing LEDs.

Therefore, this patch adds support for fractions (down to .001 seconds)
to the sleep command.

The parsing is kept minimal, simplistic and as robust as possible: After
converting the passed string using simple_strtoul and multiplying it
with 1000, we search for the first dot, convert the three characters
after that into a number (if they are not numbers, we ignore the
fractional part and just use the delay we got from simple_strtoul), and
add this number to the delay.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-07-25 12:00:05 -04:00
Steve Rae
59441ac3c1 mtd: fix compiler warnings
- add missing declaration
- update debug output format specifiers

Signed-off-by: Steve Rae <steve.rae@raedomain.com>
2016-07-24 20:36:29 -05:00
Hector Palacios
ebb7febc92 mtd: nand: fix bug writing 1 byte less than page size
nand_do_write_ops() determines if it is writing a partial page with the
formula:
	part_pagewr = (column || writelen < (mtd->writesize - 1))

When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write, although
it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating until the watchdog timeout triggers.

To reproduce the issue on a NAND with 2K page (0x800):
	=> nand erase.part <partition>
	=> nand write $loadaddr <partition> 7ff

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2016-07-24 20:36:29 -05:00
Boris Brezillon
c1aa7d629e sunxi: Enable NAND controller on the CHIP
Enable the NAND controller in the sun5i-r8-chip.dts.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:29 -05:00
Boris Brezillon
a0dfa88b4e sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS value
On some sunxi boards we have NANDs exposing 1664 OOB bytes per page.
Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-24 20:36:29 -05:00
Boris Brezillon
c1fe6b5b5e mtd: nand: Increase the max OOB size
Some NANDs are now exposing 1664 OOB bytes per page. Adjust the
NAND_MAX_OOBSIZE value accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-24 20:36:28 -05:00
Boris Brezillon
cd7f5e1cdf mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NAND
Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Maxime Ripard
32b18435de sun5i: Add NAND controller to the sun5i DTSI
Add the NAND controller definition to sun5i.dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-24 20:36:28 -05:00
Boris Brezillon
4ccae81cda mtd: nand: Add the sunxi NAND controller driver
We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.

The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00