PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
pci_hose_phys_to_bus() is needed by several drivers. Move it to
pci_common.c to avoid a broken build when CONFIG_DM_PCI is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If we are displaying detected PCI devices (CONFIG_PCI_SCAN_SHOW) display
a 'PCI:' header prior to scan.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is an existing function prototype in the header file but it is not
implemented. Implement something similar.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.
This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).
To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Previously, the address of a requested capability is define like that
"#define PCI_DCR 0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.
Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
1. Read Status register in PCIe configuration space to confirm that
Capabilities List is valid.
2. Find the address of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.
commit af778c6d9e
Author: Andrew Sharp <andywyse6@gmail.com>
Date: Wed Aug 1 12:27:16 2012 +0000
pci: fix errant data types and corresponding access functions
On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Refactor the common PCI code just a tiny bit surrounding the PCI_PNP
(pciauto) stuff. Makes the code a tiny bit easier to read, and also
makes it more obvious that almost no platform needs to setup or use the
pci_config_table stuff.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
I tried to clean up the white space and formatting offenses and
inconsistencies in the generic PCI code that obviously has been around for
some time. Emphasis on large increases in readability and maintainability
and consistency. I omitted the platform/processor specific files in
the drivers/pci directory because I wanted to leave those file to those
that care more about them.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used. Unsigned int was also being
used in a couple of places that should be pci_addr_t.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in <pci.h>
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.
Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PCI cards might need some time after reset to respond. On some
boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted
at pci_init_board() time, so we currently can not use available
"pcidelay" option for waiting before PCI bus scan since this
waiting takes place before calling pci_init_board(). By moving
the pcidelay code to the new location using of the "pcidelay"
option is possible on mpc5200 or mpc8260 based boards, too.
Since pci_hose_scan() could be called multiple times, restrict
the function to wait only during its first call and to ignore
pcidelay for any further call (as pointed out by Matthias).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead. Move board-specific PCI
setup code (clock/reset) to board directory.
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.
Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as
they are found during bootup, eg:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
This information is useful, but its difficult to determine the PCI bus
topology. To things clearer, we can use indention to make it more
obvious how the PCI bus is organized. For the example above, the
updated output with this change is:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch
(01:00 and 02:0x), which is connected to another PEX8518 PCIe switch
(06:00 and 07:0x), which then connects to a MPC8572 processor (08:00).
Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet
card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This change does the following:
- Removes the printing of the PCI interrupt line value. This is
normally set to 0 by U-Boot on bootup and is rarely used during
everyday operation.
- Prints out the PCI function number of a device. Previously a device
with multiple functions would be printed identically 2 times, which is
generally confusing. For example, on an Intel 2 port gigabit Ethernet
card the following was displayed:
...
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
...
- Prints a text description of each device's PCI class instead of the
raw PCI class code. The textual description makes it much easier to
determine what devices are installed on a PCI bus.
- Changes the general formatting of the PCI device output.
Previous output:
PCIE1: connected as Root Complex
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
Updated output:
PCIE1: connected as Root Complex
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
03:00.0 - 10b5:8112 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:00.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:01.0 - 10b5:8518 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
01:00.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Add a new 'pci enum' command which re-enumerates the PCI buses. This
command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful
in boards with FPGAs connected via PCI/PCIe, boards that support PCI
hot-plugging, or during PCI debug.
Also enable the 'pci enum' command for X-ES's Freescale-based boards.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
This is just a handy routine that reports last PCI busno: we walk
down all the hoses and return last hose's last_busno.
Will be used by PCI/PCIe initialization code.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
It is no longer always true that the pci bus address can be
used as the virtual address for pci accesses. pci_map_bar()
is created to return the virtual address for a pci region.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
When we search for an address match in pci_hose_{phys_to_bus,bus_to_phys}
we should give preference to memory regions that aren't system memory.
Its possible that we have over mapped system memory in the regions and
we want to avoid depending on the order of the regions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PCI bus is inherently 64-bit. While not all system require access to
the full 64-bit PCI address range some do. This allows those systems
to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
This patch moves the check, if a device should be skipped in PCI PNP
configuration into the function pci_skip_dev(). This function is defined
as weak so that it can be overwritten by a platform specific one if
needed. The check if the device should get printed in the PCI summary upon
bootup (when CONFIG_PCI_SCAN_SHOW is defined) is moved to the function
pci_print_dev() which is also defined as weak too.
Signed-off-by: Stefan Roese <sr@denx.de>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Physical addrs need to be represented by phys_addr_t, not
unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT
are going to fail mightily.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
In current source code, when the device number of PCI is 0, process PCI
bridge without fail. However, when the device number is 0, it is not PCI
always bridge. There are times when device of PCI allocates.
When CONFIG_PCI_SKIP_HOST_BRIDGE is enable, this problem is solved when
use this patch.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Stefan Roese <sr@denx.de>
