Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0
Commit-notes
When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c
I have a issue because gd->arch.timer_rate_hz = 0
For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.
But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.
For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.
static init_fnc_t init_sequence_f[] = {
....
arch_cpu_init_dm,
mark_bootstage, /* need timer, go after init dm */
...
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
.......
To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...
It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC
and I don't sure of impact for other function called
(board_early_init_f for example....)
=> This patch solve issue only in timer armv7
get_boot_us() can be called everytime without div by 0 issue
(gd->arch.timer_rate_hz is not used)
END
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.
Tested on custom board with AM3352 SOC and VSC801 PHY.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Testing on theadorable (Armada XP) has shown, that using this driver
results in many cache misaligned warning, such as:
CACHE: Misaligned operation at range [7fabd8fc, 7fabd900]
This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the
buffers on a cache aligned boundary. This fixes all warnings seen on the
Armada XP platform.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ted Chen <tedchen@realtek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
The most of ethernet drivers are using this mdio registration sequence.
strcpy(priv->bus->name, "emac");
mdio_register(priv->bus);
Where driver can be used only with one MDIO bus because only unique
name should be used.
Other drivers are using unique device name for MDIO registration to
support multiple instances.
snprintf(priv->bus->name, sizeof(bus->name), "%s", name);
With DM dev->seq is used more even in logs
(like random MAC address generation:
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
dev->name, dev->seq, pdata->enetaddr);
)
where eth%d prefix is used.
Simplify driver code to register mdio device with dev->seq number
to simplify mdio registration and reduce code duplication across
all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
For example:
Board: Xilinx Zynq
Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
Warning: ethernet@e000b000 (eth0) using random MAC address -
7a:fc:90:53:6a:41
eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface
rgmii-id
Warning: ethernet@e000c000 (eth3) using random MAC address -
1a:ff:d7:1a:a1:b2
, eth3: ethernet@e000c000
** Bad device size - mmc 0 **
Checking if uenvcmd is set ...
Hit any key to stop autoboot: 0
Zynq> mdio list
eth0:
17 - Marvell 88E1111S <--> ethernet@e000b000
eth3:
17 - Marvell 88E1111S <--> ethernet@e000c000
Zynq>
The dram_init* functions for the zynq board are not safe for use from
the board_init_f stage due to its use of the 'tmp' static variable.
This incorrect use of a static variable was causing rare issues where
the dram_init function would overwrite some parts the __rel_dyn section
which caused obscure failures.
Using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the "image" variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.
Uncompressing Invalid Image ... Unimplemented compression type 23
It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow.
This change removes the existing code and copies the implementation of
the dram_init and dram_init_banksize from the
arch/arm/mach-uniphier/dram_init.c source. This version of these
functions does not use static variables and behaves the same (reading
banks from fdt, and using the first bank as the ram_size).
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use embded option because of qemu
Use my repo till Stephen merge it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e80155)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).
Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c)
where file wasn't checked that it is regular file.
Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Series-to: trini
Series-cc: u-boot
All sata based drivers are bind and corresponding block
device is created. Based on this find_scsi_device() is able
to get back block device based on scsi_curr_dev pointer.
intr_scsi() is commented now but it can be replaced by calling
find_scsi_device() and scsi_scan().
scsi_dev_desc[] is commented out but common/scsi.c heavily depends on
it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol
is reassigned to a block description allocated by uclass.
There is only one block description by device now but it doesn't need to
be correct when more devices are present.
scsi_bind() ensures corresponding block device creation.
uclass post_probe (scsi_post_probe()) is doing low level init.
SCSI/SATA DM based drivers requires to have 64bit base address as
the first entry in platform data structure to setup mmio_base.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Series-changes: 2
- Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA
Ceva sata has never used sata commands that's why keep it in
SCSI part only.
- Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c
- Extend platdata
Series-changes: 3
- Fix scsi_scan return path
- Fix header location uclass-internal.h
- Add scsi_max_devs under !DM_SCSI
- Add new header device-internal because of device_probe()
- Redesign block device creation algorithm
- Use device_unbind in error path
- Create block device with id and lun numbers (lun was there in v2)
- Cleanup dev_num initialization in block device description
with fixing parameters in blk_create_devicef
- Create new Kconfig menu for SATA/SCSI drivers
- Extend description for DM_SCSI
- Fix Kconfig dependencies
- Fix kernel doc format in scsi_platdata
- Fix ahci_init_one - vendor variable
Series-changes: 4
- Fix Kconfig entry
- Remove SPL ifdef around SCSI uclass
- Clean ahci_print_info() ifdef logic
This patch adds DM support to the xHCI PCI driver. Enabling its use
e.g. in x86 platforms.
Status: On the congatec BayTrail SoM, xHCI still does not work
correctly with this patch. Some internal timeouts lead to resets (BUG).
Additional work is needed here. I'm posting this version as WIP so that
other developers interested in this support might use it as a start.
I might get back to it in a few weeks as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.
Signed-off-by: Bill Randle <bill.randle@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.
The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:
ffff0040 <data_abort>:
ffff0040: ebfffffe bl ffff0040 <data_abort>
ffff0044 <reset>:
ffff0044: ea000012 b ffff0094 <save_boot_params>
ffff0048 <save_boot_params_ret>:
ffff0048: e10f0000 mrs r0, CPSR
ffff004c: e200101f and r1, r0, #31
ffff0050: e331001a teq r1, #26
Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.
Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add the name for register space and memory space.
<0x1550000 0x10000 > is the QSPI register space.
<0x40000000 0x4000000> is the QSPI memory space.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
First of all U-Boot would search for a USB mass storage device
with either uEnv.txt or kernel-fit.itb and boot.
If USB mass storage device is not available or doesn't provide
these files then MMC will be tried.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Baltos devices provide a mPCIe slot, whose power is turned off by
default. This patch activates mPCIe slot in U-Boot, so that for example
GSM modem can be already available in user space.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom
structure. This patch makes sure that it's always read after a reset, even
if a valid MAGIC number is found in the SRAM.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The patch
"dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
(sha1: 87bce4e5c0)
converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT
part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'.
This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT
is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch fixes the warnings about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7facb400, 7facb460]
Signed-off-by: Stefan Roese <sr@denx.de>
Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch adds PCI support to the Marvell Armada-8K devel board.
Additionally the Intel E1000 ethernet driver is enabled so that
network support is available on this board, even without the
internal network interfaces being supported (yet).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
To use the PCIe driver, its controller memory and the PCIe regions need
to get mapped in the MMU. Otherwise these areas can't be accessed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.
The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.
Tested on the Marvell DB-88F8040 Armada-8K eval board.
Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
With the support for the Armada 8k, a 2nd COMPHY controller now needs
to get supported from the CP110 slave controller. This patch adds support
for this 2nd contoller in the COMPHY driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
The Armada8k implements 2 CPs (communication processors) and the 2nd
CP also is equipped with a COMPHY controller. This patch now loops
over all enabled MISC devices (CP110) enabled in the DT to initialize
all CPs.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
