Commit graph

7 commits

Author SHA1 Message Date
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Michal Simek
47446a3c66 arm: zynq: Remove low level UART setting
There is no reason to do serial initializationin low level code. Uart
driver does it already based on DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:53 +01:00
Tom Rini
f739fcd831 SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed.  These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict.  This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.

Fixes: 83d290c56f ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-10 20:38:35 -04:00
Michal Simek
460b05d96d arm: zynq: Convert all board to use arch ps7_init code
Use generic implementation. It will also reduce config data size for
converted boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
a8ea299c48 arm: zynq: Get rid of ps7_reset_apu() for syzygy board
There is no reason to call separate function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
a3b36c8424 arm: zynq: Remove ps7_debug code
SPL is not calling this code that's why it is dead code and can be
removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Tom McLeod
413ab5b0e1 arm: zynq: Add support for SYZYGY Hub board
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.

Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Michal Simek <monstr@monstr.eu>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00