Commit graph

670 commits

Author SHA1 Message Date
Simon Glass
29d2d64ed5 x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
10536ceae9 x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.

Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.

Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
26c3d3d7d5 x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard
to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
3a25073a40 x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
aec7c1c565 x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
c90b302d5f x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:21 +08:00
Simon Glass
da2c1b8fd9 x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
94c5ad2534 x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
540f0bae9b x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
9b3e6d4c1f x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
7764a8481c x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
f37979e7b7 x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.

Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
d2628984b7 x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
6c0da2da7c x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
abc585b745 x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
10552377d4 x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.

Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
59561c7c2e x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs
a few definitions to correctly set up the ACPI table. Add these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
c9cc37de2c x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
e4f09f97c9 x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo
Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
7924b499a2 x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
55109f1d4e x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.

Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
167c3f6e93 x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.

Drop the APL version as it is basically the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
13539ba705 x86: acpi: Add DPTF asl files
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
14f643d1a2 x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
d9434a17e5 x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-09-25 11:27:11 +08:00
Simon Glass
4d0c5762ad x86: acpi: Add cros_ec tables
Add ASL files for the Chrome OS EC, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
4f96023afd x86: zboot: Allow overriding the command line
When booting Chrome OS images the command line is stored separately
from the kernel. Add a way to specify this address so that images boot
correctly.

Also add comments to the zimage.h header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 8 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
631c2b9fc4 x86: zboot: Add an option to dump the setup information
There is a lot of information in the setup block and it is quite hard to
decode manually. Add a 'zboot dump' command to decode it into a
human-readable format.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
6e04cb76db x86: Update the bootparam header
This header is missing a few of the newer features from the specification.
Add these as well as a link to the spec. Also use the BIT() macros where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:06 +08:00
Simon Glass
1150a0b6bd x86: Drop nhlt_serialise()
This function is not actually used in U-Boot. Drop it.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 17:00:28 +08:00
Bernhard Messerklinger
a0186110af arch: x86: apl: Update FSP parameters
Add missing parameters to support full configuration of the latest FSP
MR6 release.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Bernhard Messerklinger
858e5a1a8b x86: apl: fsp_bindings: Add support for u64 parameters
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Wolfgang Wallner
491135805e x86: irq: Fix some typos
Fix some typos in arch/x86/include/asm/irq.h.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Simon Glass
961420fa5f cpu: Convert the methods to use a const udevice *
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-25 14:46:57 -06:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Simon Glass
f07e58b878 cpu: Convert the methods to use a const udevice *
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20 11:37:47 -06:00
Simon Glass
c6efee5031 x86: mp: Add more comments to the module
Add a description of how this module works and also some missing function
comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:48 +08:00
Simon Glass
8dda2baa97 x86: mtrr: Add support for writing to MTRRs on any CPU
To enable support for the 'mtrr' command, add a way to perform MTRR
operations on selected CPUs.

This works by setting up a little 'operation' structure and sending it
around the CPUs for action.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20 09:46:47 +08:00
Simon Glass
3d734b59c7 x86: Don't enable SMP in SPL
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL.
For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot,
but this is somewhat more complicated. For now that is disabled too.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20 09:46:46 +08:00
Simon Glass
240752c612 x86: mtrr: Use MP calls to list the MTRRs
Update the mtrr command to use mp_run_on_cpus() to obtain its information.
Since the selected CPU is the boot CPU this does not change the result,
but it sets the stage for supporting other CPUs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
0538d6833c x86: mp: Add iterators for CPUs
It is convenient to iterate through the CPUs performing work on each one
and processing the result. Add a few iterator functions which handle this.
These can be used by any client code. It can call mp_run_on_cpus() on
each CPU that is returned, handling them one at a time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
99a573fb32 x86: mp: Park CPUs before running the OS
With the new MP features the CPUs are no-longer parked when the OS is run.
Fix this by calling a special function to park them, just before the OS is
started.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
84d3ed125a x86: mp: Allow running functions on multiple CPUs
Add a way to run a function on a selection of CPUs. This supports either
a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel
terminology.

It works by writing into a mailbox and then waiting for the CPUs to notice
it, take action and indicate they are done.

When SMP is not yet enabled, this just calls the function on the main CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:45 +08:00
Simon Glass
c33aa3527d x86: mp: Support APs waiting for instructions
At present the APs (non-boot CPUs) are inited once and then parked ready
for the OS to use them. However in some cases we want to send new requests
through, such as to change MTRRs and keep them consistent across CPUs.

Change the last state of the flight plan to go into a wait loop, accepting
instructions from the main CPU.

Drop cpu_map since it is not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:45 +08:00
Simon Glass
e624858407 x86: mp_init: Avoid declarations in header files
The functions used by the flight plan are declared in the header file but
are not used in any other file.

Move the flight plan steps down to just above where it is used so that we
can make these function static.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:43 +08:00
Simon Glass
78d57d63d7 x86: Move MP code into mp_init
At present the 'flight plan' for CPUs is passed into mp_init. But it is
always the same. Move it into the mp_init file so everything is in one
place. Also drop the SMI function since it does nothing. If we implement
SMIs, more refactoring will be needed anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:42 +08:00
Simon Glass
a308b1fa39 x86: Drop setup_pcat_compatibility()
This function does not exist anymore. Drop it from the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
9ef168676c x86: Store the coreboot table address in global_data
At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.

Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(),
so it is always set when booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
b95611f67e x86: apl: Fix save/restore of ITSS priorities
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
59cf26480b x86: pinctrl: Drop the acpi_path member
This is in the device tree now, so drop the unnecessary field here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00