Commit graph

23 commits

Author SHA1 Message Date
Kumar Gala
c26de2d8b1 powerpc/p3041: Add various p3041 related defines
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Kumar Gala
19dbcc96c0 powerpc/p5020: Add various p5020 related defines (and p5010)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Becky Bruce
11a3de4697 fsl_law.c: Add print_laws() for FSL_CORENET platforms.
Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms.

Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
e71755f887 drivers/misc/fsl_law.c: Rearrange code to avoid duplication
The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Kumar Gala
216082754f 85xx: Added various P1012/P1013/P1021/P1022 defines
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-07 00:21:22 -05:00
Kumar Gala
24b17d8a3c ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPL
Don't include get_law_entry as part of the NAND_SPL build since the
code isnt used.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:12 -05:00
Kumar Gala
7e4259bba4 ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
418ec85843 ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address.  Also, the target IDs
on CoreNet platforms have been completely re-assigned.

Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.

Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Mingkai Hu
7da53351d8 ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Timur Tabi
74c5dfd81f fsl: add register read-back to set_law()
After programming a new LAW, we should read-back the LAWAR register so that
we sync the writes.  Otherwise, code that attempts to use the new LAW-mapped
memory might fail right away.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:06 -05:00
Poonam Aggrwal
a713ba926b 85xx: Added single core members of FSL P1xx/P2xx processors series
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Poonam Aggrwal
87c7661b42 85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Kumar Gala
e6a6789f41 fsl_law: Fix bug in calculation of LAW sizing
In set_ddr_laws() when we determined how much of the size requested
to be mapped was covered by the the first LAW we needed to recalculate
the size based on what was actually mapped.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-04 10:21:40 -05:00
Haiying Wang
22b6dbc169 MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30 13:33:51 -05:00
Srikanth Srinivasan
8d949aff38 mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Ed Swarthout
e1f7d22b8b fsl_law clear enable before changing.
Debug sessions may have left enabled laws.
Changing lawbar with an unkown enabled tgtid could cause problems.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Kumar Gala
ef50d6c06e mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27 11:43:54 -05:00
Kumar Gala
f784e32b4b FSL DDR: Provide a generic set_ddr_laws()
Provide a helper function that will setup the last available
LAWs (upto 2) for DDR.  Useful for SPD/dyanmic DDR setting code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 02:05:55 +02:00
Kumar Gala
ba04f70109 FSL LAW: Add new interface to use the last free LAW
LAWs have the concept of priority so its useful to be able to allocate
the lowest (highest number) priority.  We will end up using this with the
new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 01:53:09 -05:00
Kumar Gala
f060054dad FSL LAW: Keep track of LAW allocations
Make it so we keep track of which LAWs have allocated and provide
a function (set_next_law) which can allocate a LAW for us if one is
free.

In the future we will move to doing more "dynamic" LAW allocation
since the majority of users dont really care about what LAW number
they are at.

Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 01:50:53 -05:00
Becky Bruce
ddcebcb638 86xx: Add print_laws function to fsl_law.c
This can be used for debug, and will be used by board code
to help implement reginfo.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-01-24 12:12:51 -06:00
Kumar Gala
83d40dfd79 85xx: Move LAW init code into C
Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.

Board code is responsible to provide a law_table and num_law_entries.

We should be able to use the same code on 86xx as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00