The default erase command applies on erase group unit, and
simply round down to erase group size. When the start block
is not aligned to erase group size (e.g. erasing partition)
it causes unwanted erasing of the previous blocks, part of
the same erase group (e.g. owned by other logical partition,
or by the partition table itself).
To prevent this issue, a simple solution is to use TRIM as
argument of the Erase command, which is usually supported
with eMMC > 4.0, and allow to apply erase operation to write
blocks instead of erase group
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
When secure/insecure TRIM operations are supported.
When used as erase command argument it applies the
erase operation to write blocks instead of erase
groups.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
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Merge tag 'video-20230407' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix building sandbox without SDL
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Re-use simple panel driver for MIPI DSI panels
which do not require additional DSI commands
for setup.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Some cases may require passing display timings from
panel driver. To handle such cases support parsing
device tree panel node for timing subnode.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features
like ganged mode won't work. Driver is heavily based on
mainline Tegra DSI and re-uses much of its features.
Only T30 is supported for now but T20 support can be added
if any supported devices will be found.
Driver is wrapped as panel driver since Tegra DC driver supports
only panel drivers calls.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Internal video devices like DSI and HDMI controllers
require sending commands into DC register field.
To make this available, lets create platform data,
which is restricted to pass DC regmap only to
pre-defined devices.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra DC driver does not call panel_set_backlight, which can
result in absence of backlight on device. Fix this by calling
panel_set_backlight with BACKLIGHT_DEFAULT just after
panel_enable_backlight.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Unlike 90 and 270 degree rotation, 180 degree rotation is more
common and does not require scaling. Implement it for correct
grouper support.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # Google Nexus 7 2012
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Check if panel driver has display timings and get those.
If panel driver does not pass timing, try to find timing
under rgb node for backwards compatibility.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
DISP1 clock may use PLLP, PLLC and PLLD as parents.
Instead of hardcoding, lets pass clock and its
parent from device tree. Default parent is PLLP.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Move tegra dc driver to tegra20 directory and also mention
T30 in description of the driver's config option.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
[agust: add commit description]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add pinctrl tables for R8A779G0 V4H SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, sort sh_pfc_pinconf_set voltage args]
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
Add pinctrl tables for R8A779F0 S4 SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
Add clock tables for R8A779F0 S4 SoC
Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.
This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.
The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.
This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Provide the basic HSCIF support for R-Car SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Fill in HSSRR offset for Gen2 and SCBRR calculation for Gen2 and Gen3]
Reviewed-by: Simon Glass <sjg@chromium.org>
Add R-Car Gen4 family support. The basic function is as same as previous
R-Car Generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Swap RZ/A1 and Gen4 to keep the GenN sequence, use RCAR_64]
Add support for R-Car Gen4 SoCs and a matching DT compatible.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop SoC specific compatible, use RCAR_64 Kconfig symbol, update commit message]
Support R-Car Gen4 family. The default quirk is similar to previous
generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros.
This improves build test coverage. The CONFIG_SPL_BUILD must remain an
ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot
proper build. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The 64bit limitation check is compiled and optimized out on 32bit
platforms, but generates a type width warning:
drivers/mmc/tmio-common.c: In function ‘tmio_sd_addr_is_dmaable’:
drivers/mmc/tmio-common.c:376:26: warning: right shift count >= width of type [-Wshift-count-overflow]
376 | if (addr >> 32)
| ^~
Fix the warning by checking the addr type width to see whether the
shift even makes sense in the first place. The width check is also
optimized out at compile time.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add support for R-Car Gen4 SoCs into the driver.
While I2C on R-Car Gen4 does support some extra features (Slave Clock
Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
which let us share the same driver.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for the GPIO controller block in the R-Car Gen4 family.
It has a General Input Enable Register (INEN), whose reset state is to
have all inputs disabled.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add two new callbacks matching the Linux ones. The .set_mode is used to set
PHY mode and submode, where mode is either USB, Ethernet, and so on, while
submode is e.g. for Ethernet case RGMII, RMII, and so on. The .set_speed is
used to configure link speed into the PHY. Unlike the existing configure
callback, which is used to pass arbitrary custom information to the PHY,
these two callbacks are used to pass standardized set of information to
the PHY.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Pull Marvell 10G PHY driver from Linux 6.1.y as of commit
d6d29292640d3 ("net: phy: marvell10g: select host interface configuration")
and heavily adapt to match U-Boot PHY framework. Support for
hwmon is removed as is much other functionality which could
not be tested, this results in much simpler driver which can
only bring the PHY up and set MAC type.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add phy_modify_mmd()/phy_modify_mmd_changed() from Linux 5.1.y as of commit
b8554d4f7288f ("net: phy: add register modifying helpers returning 1 on change")
This is used by the upcoming Marvell 10G PHY driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Import marvell_phy.h from Linux 5.14.y as of commit
a5de4be0aaaa6 ("net: phy: marvell10g: fix differentiation of 88X3310 from 88X3340")
and use it in marvell PHY driver instead of current ad-hoc macros.
Two of the PHY IDs are unknown to Linux, 88E1149S and 88E1680, for
those two, only sync the length of the hexadecimal number to 8 digits.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Synchronize PHY interface modes with Linux next 6.2.y commit:
0194b64578e90 ("net: phy: improve phy_read_poll_timeout")
Retain LX2160A/LX2162A PHY modes as those are not yet supported
by the Linux kernel, but isolate those with ifdeffery.
Isolate NCSI which are also not supported by Linux kernel. Note
that the ifdeffery cannot be avoided with IS_ENABLED() here due
to compilation of the entire conditional, which would fail in
case NCSI symbols are not available.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Replace PHY_INTERFACE_MODE_SFI with PHY_INTERFACE_MODE_5GBASER,
PHY_INTERFACE_MODE_10GBASER and PHY_INTERFACE_MODE_XAUI to match
Linux PHY interface modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This mode does not seem to be well defined and used anywhere, remove support for it.
Based on discussion:
- 1000baseX does c37 AN of duplex+pause
- SGMII does AN of duplex+pause+speed, at lower speed bytes are repeated 10x/100x
- 2500baseX does not do AN, or does very different c73 AN
- SGMII 2500 behavior is unclear
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The phy_init() is now used only to perform manual relocation of PHY
driver callbacks. Wrap it in ifdeffery and only call it on systems
which still require manual relocation, i.e. m68k .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Wrap phy_drv_reloc() back into phy_init() to reduce ifdeffery,
since phy_drv_reloc() is now called only from one call site.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
This function is no longer used, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
The static phy_drivers list is superseded by linker list of struct phy_drivers
now that all drivers have been converted to the later. Drop the phy_drivers
list as well as list_head from struct phy_driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
