Commit graph

22102 commits

Author SHA1 Message Date
Takumi Sueda
db2c8ed3a5 video: simplefb: add rotation support
It introduces the way to rotate the screen for boards with rotated screen.

Signed-off-by: Takumi Sueda <puhitaku@gmail.com>
2022-10-30 08:28:40 +01:00
John Keeping
7209272497 video: dw_mipi_dsi: fix [hv]sync active vs back porch
The wrong fields are pulled out of the timings here so the values
programmed into the DSI_VID_HSA_LINES/DSI_VID_HBP_LINES and
DSI_VID_VSA_LINES/DSI_VID_VBP_LINES registers are swapped.

Use the right fields so that the correct values are programmed.

Fixes: d4f7ea83fc ("video: add MIPI DSI host controller bridge")
Signed-off-by: John Keeping <john@metanate.com>
2022-10-30 08:19:45 +01:00
Michal Suchanek
f21954750a dm: core: Do not stop uclass iteration on error
When probing a device fails NULL pointer is returned, and following
devices in uclass list cannot be iterated. Skip to next device on error
instead.

With that the only condition under which these simple iteration
functions return error is when the dm is not initialized at uclass_get
time. This is not all that interesting, change return type to void.

Fixes: 6494d708bf ("dm: Add base driver model support")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 07:36:33 -06:00
Michal Suchanek
4954937d92 dm: treewide: Do not use the return value of simple uclass iterator
uclass_first_device/uclass_next_device return value will be removed,
don't use it.

With the current implementation dev is equivalent to !ret. It is
redundant to check both, ret check can be replaced with dev check, and
ret check inside the iteration is dead code.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 07:36:33 -06:00
Michal Suchanek
58ddb937e1 dm: core: Switch uclass_*_device_err to use uclass_*_device_check
Clarify documentation, fix a few more cases that could be broken by the
change.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2022-10-29 07:36:33 -06:00
William Zhang
6792bd999b dm: tpl: Add fdt address translation support in TPL
This is needed in the platforms that use "ranges" node property for
address translation in their dts for TPL.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 07:36:33 -06:00
Simon Glass
d138792112 dm: core: Fix lists_bind_fdt() using non-existent of_match
The call to device_bind_with_driver_data() passes id->data but if
the entry has no of_match then the id has not been set by the selected
driver.

Normally this passes unnoticed since a previous driver likely had an
of_match value, so the id is set to that. Of course it is not correct
to pass the id->data from a different driver.

With clang-14 the driver ordering is such that the id is never actually
set in the 'bind /usb@1 usb_ether' line in test_bind_unbind_with_node()
thus causing a crash.

Fix this by passing 0 if the of_match for a driver does not exist.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-29 07:36:33 -06:00
Rasmus Villemoes
10e66449d7 gpio-uclass: fix gpio lookup by label
Matching anything that just happens to have the sought-for label as a
prefix is wrong. For example, if the board designer has designated 10
lines for debug purposes, named "debug1" through "debug10", and we are
looking up "debug1", if debug10 happens to be met first during the
iteration we'd wrongly return that.

In theory, this can break existing users that could rely on this
quirk, but OTOH keeping the current broken semantics can cause a lot
of grief for people hitting this in the future and not understanding
why they don't find the line they expect. Considering how few in-tree
defconfigs currently set DM_GPIO_LOOKUP_LABEL (ignoring sandbox, only
four "real" boards), let's fix it before the use becomes more
widespread.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-10-29 07:36:33 -06:00
Jim Liu
c1dc8473fa spi: nuvoton: add NPCM PSPI controller driver
Add Nuvoton NPCM BMC Peripheral SPI controller driver.
NPCM750 include two general-purpose SPI interface.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-27 12:41:36 +05:30
Roger Quadros
9b0b5648d6 memory: Add TI GPMC driver
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
 - Asynchronous SRAM-like memories and ASICs
 - Asynchronous, synchronous, and page mode burst NOR flash
 - NAND flash
 - Pseudo-SRAM devices

This driver will take care of setting up the GPMC based on
the settings specified in the Device tree and then
probe its children.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2022-10-26 15:21:12 -04:00
Roger Quadros
2c120375e9 dm: memory: Introduce new uclass
Introduce UCLASS_MEMORY for future Memory Controller
device drivers.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-26 15:21:11 -04:00
Benjamin Bara
b567eae0c5 crypto: hash: sw: fix Kconfig dependencies
Fix SHA512 config name and add missing SHA384 config.

Signed-off-by: Benjamin Bara <Benjamin.Bara@skidata.com>
2022-10-26 15:21:11 -04:00
Tom Rini
b487387226 Merge https://source.denx.de/u-boot/custodians/u-boot-pmic 2022-10-26 07:46:48 -04:00
Tom Rini
c2c485db45 Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- nuvoton: add expire function for generic reset (Jim)
- handle watchdogs during keyed autoboot (Rasmus)
- cyclic: Don't disable cylic function upon exceeding CPU time (Stefan)
- ulp wdog: Updates to support iMX93 and DM (Alice)
2022-10-26 07:45:55 -04:00
Michal Suchanek
0b9186277a power: fan53555: Fix missing newline in error message
Avoid concatenation with following message.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-26 11:47:25 +09:00
John Keeping
8edf7ac09f power: regulator: fix autoset error handling
If a regulator does not support .set_suspend_enable or
.set_suspend_value then ret is set to ENOSYS early in the function.

The most serious impact of this is that when no automatic setting of
voltage is needed then the final regulator_set_enable() is skipped
because ret has not been cleared.

It seems that the error handling for regulator_set_suspend_value() is
also wrong as if this succeeds then the normal boot-on checks are still
required, and again ENOSYS needs special treatment here.

Fixes: 11406b8f7e ("dm: regulator: support regulator more state")
Signed-off-by: John Keeping <john@metanate.com>
2022-10-26 11:47:12 +09:00
Tom Rini
f9d16f2c0d Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- Add s28hl512t, s28hl01gt (Takahiro)
- Rework s25hx_t_post_bfpt_fixup() (Takahiro)
2022-10-25 09:54:59 -04:00
Tom Rini
26bfb853ca Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc 2022-10-24 21:28:14 -04:00
Tom Rini
7d8ab3cd63 u-boot-imx-20221024
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916
 
 - for 2022.01
 - rework Kontron boards (mx6 and mx8)
 - fixes for Toradex
 - fixes (SPI, CAAM, )
 - sync DT with Linux
 - fixes for Gateworks GW7903 and GW7904 PMIC
 - Engicam i.Core MX8M Plus EDIMM2.2
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCY1aVgA8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76YlhwCfXTQJzJXruk6UKg1zbsimD3bsChUAoJFzB3yp
 zft+THzNdQTnfUGN9u+U
 =JHxW
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20221024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916

- for 2022.01
- rework Kontron boards (mx6 and mx8)
- fixes for Toradex
- fixes (SPI, CAAM, )
- sync DT with Linux
- fixes for Gateworks GW7903 and GW7904 PMIC
- Engicam i.Core MX8M Plus EDIMM2.2
2022-10-24 10:04:30 -04:00
Rasmus Villemoes
c9473b2c37 imx8m: fix reading of DDR4 MR registers [again]
Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.

However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].

I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.

So apply the fix from 290ffe5788 once again.

Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-24 11:34:33 +02:00
Alice Guo
5e112c7ca8 watchdog: ulp_wdog: add driver model for ulp watchdog driver
Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the
status of device node is "okay", initr_watchdog will be called and
finally calls ulp_wdt_probe() and ulp_wdt_start().

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Alice Guo
a7fd633501 watchdog: ulp_wdog: enable watchdog interrupt on imx93
The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the
source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset
needs to enable the watchdog interrupt.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Alice Guo
ef0ad9b07d watchdog: ulp_wdog: Update watchdog driver for imx93
The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the
timeout period exceeds 2 seconds, the value written to the TOVAL
register is larger than 16-bit can represent. Enabling watchdog
prescaler to solve this problem.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Ye Li
a79f2007d0 ulp_wdog: Update ulp wdog driver for 32bits command
To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Rasmus Villemoes
10107efedd sandbox: add SIGALRM-based watchdog device
In order to test that U-Boot actually maintains the watchdog device(s)
during long-running busy-loops, such as those where we wait for the
user to stop autoboot, we need a watchdog device that actually does
something during those loops; we cannot test that behaviour via the DM
test framework.

So introduce a relatively simple watchdog device which is simply based
on calling the host OS' alarm() function; that has the nice property
that a new call to alarm() simply sets a new deadline, and alarm(0)
cancels any existing alarm. These properties are precisely what we
need to implement start/reset/stop. We install our own handler so that
we get a known message printed if and when the watchdog fires, and by
just invoking that handler directly, we get expire_now for free.

The actual calls to the various OS functions (alarm, signal, raise)
need to be done in os.c, and since the driver code cannot get access
to the values of SIGALRM or SIG_DFL (that would require including a
host header, and that's only os.c which can do that), we cannot simply
do trivial wrappers for signal() and raise(), but instead create
specialized functions just for use by this driver.

Apart from enabling this driver for sandbox{,64}_defconfig, also
enable the wdt command which was useful for hand-testing this new
driver (especially with running u-boot under strace).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-10-24 11:10:21 +02:00
Rasmus Villemoes
2783670583 watchdog: introduce a u-boot,autostart property
This is a companion to u-boot,noautostart. If one has a single
watchdog device that one does want to have auto-started, but several
others that one doesn't, the only way currently is to set the
CONFIG_WATCHDOG_AUTOSTART and then use the opt-out for the majority.

The main motivation for this is to add an autostarted watchdog device
to the sandbox (to test a fix) without having to set AUTOSTART in
sandbox_defconfig and add the noautostart property to the existing
devices. But it's also nice for symmetry, and the logic in
init_watchdog_dev() becomes simpler to read because we avoid all the
negations.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-10-24 11:09:19 +02:00
Jim Liu
0ab55cb6f7 wdt: nuvoton: add expire function for generic reset
Add expire_now function for generic sysreset request

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-24 11:06:24 +02:00
Venkatesh Yadav Abbarapu
337af54a36 mmc: Fix static checker warnings
Correct pointer dereferencing check to be more consistent.

Eliminate the below smatch warning:
drivers/mmc/mmc.c:3118 mmc_init_device()
warn: variable dereferenced before check 'm' (see line 3116)

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:54 +09:00
John Keeping
7ff2f30b63 mmc: dwmmc: only clear handled interrupts
Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:

	mask = dwmci_readl(host, DWMCI_RINTSTS);

	// Hardware asserts DWMCI_INTMSK_DTO here

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);

	if (mask & DWMCI_INTMSK_DTO) {
		// Unreachable as DTO is cleared without being handled!
		return 0;
	}

Only clear interrupts that we have seen and are handling so that DTO is
not missed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B)
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:41 +09:00
Yann Gautier
359c176de5 mmc: stm32_sdmmc2: manage vqmmc
The SDMMC IOs can be in an IO domain, that has to be enabled.
This is done by enabling vqmmc in the driver.
This has no impact on configurations not using an IO domain, the check
can then be executed on all platforms managing regulator, and the vqmmc
regulator enabled on all platforms having it in their DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:15 +09:00
Yann Gautier
27fbce4326 mmc: stm32_sdmmc2: protect against unsupported modes
The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:07 +09:00
Yann Gautier
be1872982e mmc: stm32_sdmmc2: add dual data rate support
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:59 +09:00
Kunihiko Hayashi
12fc8efe5a mmc: f_sdh30: Add support for F_SDH30_E51
Add Socionext F_SDH30_E51 IP support. The features of this IP includes
CMD/DAT line delay and force card insertion mode for non-removable cards.
And the IP needs to add some quirks.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2022-10-24 18:01:32 +09:00
Kunihiko Hayashi
2b0dd4174f mmc: sdhci: Add new quirks for SUPPORT_SINGLE
This patch defines a quirk to disable the block count
for single block transactions.

This is similar to Linux kernel commit d3fc5d71ac4d
("mmc: sdhci: add a quirk for single block transactions").

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:23 +09:00
Sergei Antonov
fc6b5d8260 mmc: ftsdc010: make command timeout 250 ms as in the comment
Get rid of discrepancy beween comment /* 250 ms */ and code
which shifts by 4 thus dividing by 16.
So change code to shift by 2 and make the timeout value 250 ms.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:07 +09:00
Takahiro Kuwano
e28d3ead72 mtd: spi-nor-core: Fix index value for SCCR dwords
Array index for SCCR 22th DWORD should be 21.

Fixes: bebdc23750 ("mtd: spi-nor: Parse SFDP SCCR Map")
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:52:16 +05:30
Takahiro Kuwano
7a4b6f8cf7 mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode
The flash's internal address mode is tracked by nor->add_mode_nbytes and
it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are
3- or 4-byte address mode by default, depending on model number. We need
to make sure that 4-byte address mode is used for multi-die package parts.

For single-die package parts (<=1Gb), registers can be accessed by 3-byte
address. Read, program, and erase use the 4B opcodes that always take
4-byte address regardless of flash's internal address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:38 +05:30
Takahiro Kuwano
f58e7b24fa mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes
Read/Write Any Register commands take 3- or 4- byte address depending on
flash's internal address mode. The nor->addr_width tracks number of
address bytes used in read/program/erase ops that can be 4
(with 4B opcodes) regardless of flash's internal address mode. The
nor->addr_mode_nbytes tracks flash's internal address mode so replace
nor->addr_width by that.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:26 +05:30
Takahiro Kuwano
4d60001fdf mtd: spi-nor-core: Track flash's internal address mode
The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:17 +05:30
Takahiro Kuwano
ee1c709cfd mtd: spi-nor-core: Default to addr_width of 3 for configurable widths
JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on
command."

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:04 +05:30
Takahiro Kuwano
de9e8378a8 mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs
Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt.
These devices have the same functionality as s28hs512t.

In spi-nor-core, use device ID byte to detect S28 family instead of
device name.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:43 +05:30
Takahiro Kuwano
f422c4bec7 mtd: spi-nor-core: Rename configuration macro for S28 support
Change configuration macro name to support all other devices in SEMPER S28
family.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:28 +05:30
Takahiro Kuwano
4bfeb00cc1 mtd: spi-nor-core: Rename s28hs512t prefix
Change prefix to support all other devices in SEMPER S28 family.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:15 +05:30
Alice Guo
71858454fe gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller
Add gpio driver for ADP5585 I/O Expander Controller. The ADP5585 is a 10
input/output port expander and can be used to increase the number of
I/Os available to a processor.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-10-21 16:06:13 -04:00
Samuel Mendoza-Jonas
3b400e84ba net/ftgmac100: Add NC-SI mode support
Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.

NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio setup is
skipped in favour of the NC-SI phy.

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-21 16:04:39 -04:00
Samuel Mendoza-Jonas
09bd3d0b0a net: NC-SI setup and handling
Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-21 16:04:39 -04:00
Tom Rini
f60e6f6767 input: Remove legacy KEYBOARD option
There are no platforms that have not migrated to using DM_KEYBOARD,
remove the legacy option.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-21 13:47:56 -04:00
Tom Rini
9af4a0c8a6 core: Enable DM by default
There are no longer any platforms which do not enable DM, move this to a
def_bool y and remove the check in the Makefile.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-21 13:47:56 -04:00
Ye Li
eda25c11b8 crypto/fsl: fsl_rsa: Fix dcache issue in the driver
issue:
CAAM fails with key error when perform Modular Exponentiation
using PKHA Block in CAAM

Fix:
add flush and invalidate dcache for keys, signature
and output decrypted data processed by CAAM.

Fixes: 34276478f7 (DM: crypto/fsl - Add Freescale rsa DM driver)
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-10-21 11:54:13 +02:00
Fabio Estevam
1703a7c4c2 clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=y
The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the
QSPI clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
4ede070601 clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=y
The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the
ecspi clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
0d158e0181 clk-imx8mm: Move CLK_ENET_AXI to the non-SPL section
Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock
inside the non-SPL block to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
d63dc069ee clk-imx8mm: Only build PWM clocks in non-SPL code
PWM is not used inside SPL, so do not define the PWM clocks inside
SPL to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Ye Li
e0709aff27 mmc: fsl_esdhc: fix problem when using clk driver
Move init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-21 11:54:13 +02:00
Tom Rini
145a996592 Merge tag 'u-boot-rockchip-20221020' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- dts update and sync for rk356x, rk3288, rk3399 from Linux;
- Add rk3399 EAIDK-610 board support;
- Update for puma-rk3399 board;
- some fix and typo fix in different drivers;
2022-10-20 22:32:38 -04:00
Tom Rini
d843273a80 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2022-10-20 09:11:08 -04:00
Tom Rini
dc3cb0abf4 Clock patches for 2023.01
This contains various fixes (some long overdue) for the next release.
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Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clk

Clock patches for 2023.01

This contains various fixes (some long overdue) for the next release.
2022-10-20 08:58:25 -04:00
Tom Rini
73ceadcd72 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Beside some rather unexciting sync of the DTs from the kernel tree, and
some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner
family, to support boards with the F1C200s (64MB DRAM) better. We will
get actual board support as soon as the DTs have passed the Linux review
process.
There is also support for the X96 Mate TV Box, featuring the H616 SoC and
a full 4GB of DRAM.
Also we found the secret to enable SPI booting on the H616 (pin PC5 must
be pulled to GND), so the SPI boot support patch is now good to go.

Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
X96 Mate and OrangePi Zero.
2022-10-20 08:58:05 -04:00
Heinrich Schuchardt
e77ef0bb74 k210: fix k210_pll_calc_config()
The k210 driver is selected by sandbox_defconfig.
Building the sandbox on 32bit systems fails with:

test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’:
include/linux/bitops.h:11:38: warning:
left shift count >= width of type [-Wshift-count-overflow]
   11 | #define BIT(nr)         (1UL << (nr))
      |                              ^~
test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’
   36 |                         error = abs((error - BIT(32))) >> 16;
      |                                              ^~~

Use the BIT_ULL() macro to create a u64 value.
Replace abs() by abs64() to get correct results on 32bit system
Apply the same for the unit test.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-10-20 15:22:30 +08:00
Patrick Delaunay
19fb40a5e7 clk: update clk_clean_rate_cache to use private clk struct
In clk_clean_rate_cache, clk->rate should update the private clock
struct, in particular when CCF is activated, to save the cached
rate value.

When clk_get_parent_rate is called, the cached information
is read from pclk->rate, with pclk = clk_get_parent(clk).

As the cached is read from private clk data, the update should
be done also on it.

Fixes: 6b7fd3128f ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid
Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-10-19 12:28:30 -04:00
Michal Suchanek
aa36a74f0f rockchip: clk: pll: Fix constant typo
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
2022-10-19 12:06:48 -04:00
Michal Suchanek
a1265cd580 clk: change return type of clk_get_parent_rate from long long to ulong
All functions getting and setting clock rate use ulong for rate, only
clk_get_parent_rate is an exception. Change the return value to match
other clock rate funcrions.

Most users directly assign the rate to unsigned long anyway, and the few
users that use u64 (not s64) multiply the rate so they may need the
extra bits for the result in their use case.

Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220928103757.11870-1-msuchanek@suse.de
2022-10-19 12:06:41 -04:00
Andre Przywara
843ed983a0 suniv: add UART1 support
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19 14:15:02 +01:00
Quentin Schulz
d842b561bb ram: rockchip: fix typo in KConfig option label
RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo.

Fixes: 2db36c64bd ("ram: rockchip: px30: add a config-based ddr selection")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Xavier Drudis Ferran
2cb23b80e4 arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range
The original code set up the DDR clock to 48 MHz, not 50MHz as
requested, and did it in a way that didn't satisfy the Application
Notes in RK3399 TRM [1]. 2.9.2.B says:

   PLL frequency range requirement
   [...]
   FOUTVCO: 800MHz to 3.2GHz

2.9.2.A :
   PLL output frequency configuration
   [...]
   FOUTVCO = FREF / REFDIV * FBDIV
   FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2

FREF = 24 MHz

The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz
And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz
but the requested frequency was 50MHz

Note:
2.7.2 Detail Register Description
PMUCRU_PPLL_CON0 says

   fbdiv
   Feedback Divide Value
   Valid divider settings are:
   [16, 3200] in integer mode

So .fbdiv = 12 wouldn't be right. But 2.9.2.C says:

   PLL setting consideration
   [...]
   The following settings are valid for FBDIV:
   DSMPD=1 (Integer Mode):
   12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600
   (FVCOMAX / FREFMIN))
   [...]

So .fbdiv = 12 would be right.

In any case FOUTVCO is still wrong. I thank YouMin Chen for
confirmation and explanation.

Despite documentation, I don't seem to be able to reproduce a
practical problem with the wrong FOUTVCO. When I initially found it I
thought some problems with detecting the RAM capacity in my Rock Pi 4B
could be related to it and my patch seemed to help. But since I'm no
longer able to reproduce the issue, it works with or without this
patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses
this issue. Btw, shouldn't that be commited?

So this patches solves no visible problem.  Yet, to prevent future
problems, I think it'd be best to stick to spec.

An alternative to this patch could be

    {.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6};

This would theoretically consume more power and yield less jitter,
according to 2.9.2.C :

   PLL setting consideration
   [...]
   For lowest power operation, the minimum VCO and FREF frequencies
   should be used. For minimum jitter operation, the highest VCO and
   FREF frequencies should be used.
   [...]

But I haven't tried it because I don't think it matters much. 50MHz
for DDR is only shortly used by TPL at RAM init. Normal operation is
at 800MHz.  Maybe it's better to use less power until later when more
complex software can control batteries or charging or whatever ?

Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>

Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766

Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Tested-by: Michal Suchánek <msuchanek@suse.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Tom Rini
d8a1a68124 watchdog: omap_wdt: Switch required include for watchdog defines
All of the required values for using the omap_wdt.c driver are found in
<asm/ti-common/omap_wdt.h> and this is what is indirectly pulled in via
<asm/arch/hardware.h> when it exists.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-10-18 13:40:40 -04:00
Andrew Davis
b9add6413d dma: Transfer dma_ops should use DMA address types
DMA operations should function on DMA addresses, not virtual addresses.
Although these are usually the same in U-Boot, it is more correct
to be explicit with our types here.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Andrew Davis
b839265046 dma: ti-edma3: Add DMA map operations before and after transfers
We should clean the caches before any DMA operation and clean+invalidate
after. This matches what the DMA framework does for us already but adds
it to the two functions here in this driver that don't yet go through the
new DMA framework.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Andrew Davis
c8d2fc7517 dma: Use dma-mapping for cache ops and sync after write
The DMA'd memory area needs cleaned and invalidated after the DMA
write so that any stale cache lines do not mask new data.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Matt Ranostay
28ba10074b phy: ti: j721e-wiz: add j784s4-wiz-10g module support
Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
2022-10-18 09:48:22 -04:00
Michal Suchanek
e44d7e73fe dm: core: Switch uclass_*_device_err to use uclass_*_device_check
The _err variant iterators use the simple iterators without suffix as
basis.

However, there is no user that uclass_next_device_err for iteration,
many users of uclass_first_device_err use it to get the first and
(assumed) only device of an uclass, and a couple that use
uclass_next_device_err to get the device following a known device in the
uclass list.

While there are some truly singleton device classes in which more than
one device cannot exist these are quite rare, and most classes can have
multiple devices even if it is not the case on the SoC's EVB.

In a later patch the simple iterators will be updated to not stop on
error and return next device instead. With this in many cases the code
that expects the first device or an error if it fails to probe may get
the next device instead. Use the _check iterators as the basis of _err
iterators to preserve the old behavior.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
801f71194c dm: core: Switch uclass_foreach_dev_probe to use simple iterator
The return value is not used for anythig, and in a later patch the
behavior of the _err iterator will change in an incompatible way.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update pvblock_probe() to avoid using internal var:
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
9b7474d83b dm: blk: Do not use uclass_next_device_err
blk_first_device_err/blk_next_device_err uses
uclass_first_device_err/uclass_next_device_err for device iteration.

Although the function names superficially match the return value from
uclass_first_device_err/uclass_next_device_err is never used
meaningfully, and uclass_first_device/uclass_next_device works equally
well for this purpose.

In the following patch the semantic of
uclass_first_device_err/uclass_next_device_err will be changed to be
based on uclass_first_device_check/uclass_next_device_check breaking
this sole user that uses uclass_next_device_err for iteration.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
c726fc01cf dm: treewide: Use uclass_first_device_err when accessing one device
There is a number of users that use uclass_first_device to access the
first and (assumed) only device in uclass.

Some check the return value of uclass_first_device and also that a
device was returned which is exactly what uclass_first_device_err does.

Some are not checking that a device was returned and can potentially
crash if no device exists in the uclass. Finally there is one that
returns NULL on error either way.

Convert all of these to use uclass_first_device_err instead, the return
value will be removed from uclass_first_device in a later patch.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
9244645f92 w1: Fix bus counting in w1_get_bus
Use uclass_first_device_check/uclass_next_device_check to correctly
count buses that fail to probe.

Fixes: d3e19cf919 ("w1: Add 1-Wire uclass")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
f426423471 video: ipuv3: Fix error handling when getting the display
The code checks that uclass_first_device returned a device but the
returned value that is assigned is never used. Use
uclass_first_device_err instead, and move the error return outside of
the if block.

Fixes: f4ec1ae08e ("mxc_ipuv3_fb.c: call display_enable")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
2cb43ef1c2 usb: ether: Fix error handling in usb_ether_init
The code checks the return value from uclass_first_device as well as
that the device exists but it passes on the return value which may be
zero if there are no gadget devices. Just check that a device was
returned and return -ENODEV otherwise.

Also remove the dev variable which is not really used for anything.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
5afe93a18c dm: pci: Fix device PCI iteration
When there is no PCI bus uclass_first_device will return no bus and no
error which will result in pci_find_first_device calling
skip_to_next_device with no bus, and the bus is only checked at the end
of the while cycle, not the beginning.

Fixes: 76c3fbcd3d ("dm: pci: Add a way to iterate through all PCI devices")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
c0648b7b9d dm: treewide: Do not opencode uclass_probe_all()
We already have a function for probing all devices of a specific class,
use it.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
dfecd63192 dm: core: Fix uclass_probe_all to really probe all devices
uclass_probe_all uses uclass_first_device/uclass_next_device assigning
the return value.

The interface for getting meaningful error is
uclass_first_device_check/uclass_next_device_check, use it.

Also do not stop iteration when an error is encountered. Probing all
devices includes those that happen to be after a failing device in the
uclass order.

Fixes: a59153dfeb ("dm: core: add function uclass_probe_all() to probe all devices")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Simon Glass
e21ec17d42 dm: regmap: Disable range checks in SPL
A recent change to regmap breaks building of phycore-rk3288 for me. The
difference is only a few bytes. Somehow CI seems to pass, even though it
fails when I run docker locally. But it prevents me from sending any more
pull requests.

In any case this board is clearly near the limit. We could revert the
offending change, but it is needed for sandbox tests.

Instead, add a way to drop the range checks in SPL, since they end up
doing nothing if everything is working as expected.

This makes phycore-rk3288 build again for me and reduces the size of SPL
slightly for a number of boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 947d4f132b ("regmap: fix range checks")
2022-10-17 21:17:12 -06:00
Paul Barker
c98f6fed93 spi: Implement spi_set_speed
This function is already defined in spi.h but no implementation of it
currently exists in the tree. The implementation is based on the static
function spi_set_speed_mode(). The function prototype is modified so
that an success or error condition can be returned to the caller.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-10-16 12:23:22 +02:00
Ignacio Zamora
34803205eb Fix typo in CONFIG_USBNET_DEVADDR
Fix typo that was caused by the same feature being split in to 2 different
configuration options. Replace CONFIG_USBNET_DEVADDR with
CONFIG_USBNET_DEV_ADDR

Signed-off-by: Ignacio Zamora <nachopitt@gmail.com>
2022-10-12 11:11:19 -04:00
Robert Marko
ce1df11bf4 smem: msm: add missing <linux/sizes.h>
MSM SMEM driver is currently missing <linux/sizes.h> header and throws
the following compile error:

drivers/smem/msm_smem.c: In function ‘qcom_smem_get_ptable’:
drivers/smem/msm_smem.c:635:71: error: ‘SZ_4K’ undeclared (first use in this function)
  635 |         ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K;

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: luka.perkov@sartura.hr
2022-10-12 08:56:24 -04:00
Patrick Delaunay
eebb967dce firmware: scmi: fix the multi channel support with CCF
When the CCF is activated, the dev->parent is not necessary
the reference to SCMI transport and the function devm_scmi_of_get_channel
failed for the registered SCMI clock, child for protocol@14,
the channel is null and the SCMI clock driver crash for any operations.

This patch changes the first parameter of the ops of_get_channel(),
aligned with other process_msg() to pass directly the good reference,
i.e. parent result of find_scmi_transport_device(dev)
which return the reference of the scmi transport device.

Fixes: 8e96801aa6 ("firmware: scmi: add multi-channel support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-10-12 08:55:31 -04:00
Robert Marko
1fad2cb852 thermal: add sandbox driver
Provide a simple sandbox driver for the thermal uclass.
It simply registers and returns 100 degrees C if requested.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-11 16:03:03 -04:00
John Keeping
7eda1a9533 pinctrl: fix buffer size for pinctrl_generic_set_state_prefix()
This buffer has the concatenated prefix and name written into it, so it
must be large enough to cover both strings plus the terminating NUL.

Fixes: 92c4a95ec7 ("pinctrl: Add new function pinctrl_generic_set_state_prefix()")
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-11 15:40:48 -04:00
Jim Liu
45455e8ff5 pinctrl: nuvoton: fix set persist error
CA9C is cortex A9 watchdog reset control bit.
if device set persist mode, it shouldn't set this bit.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-11 15:40:48 -04:00
Philip Oberfichtner
bda5f3e7d6 bootcount: pmic: Correct misleading comment
Fix a copy-paste error I did when inserting the comment.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-11 15:40:48 -04:00
Tom Rini
300077cf8c Xilinx changes for v2023.01-rc1 (round 3)
fpga:
 - Create new uclass
 - Get rid of FPGA_DEBUG and use logging infrastructure
 
 zynq:
 - Enable early EEPROM decoding
 - Some DT updates
 
 zynqmp:
 - Use OCM_BANK_0 to check config loading permission
 - Change config object loading in SPL
 - Some DT updates
 
 net:
 - emaclite: Enable driver for RISC-V
 
 xilinx:
 - Fix static checker warnings
 - Fix GCC12 warning
 
 sdhci:
 - Read PD id from DT
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Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT
2022-10-11 09:57:08 -04:00
Mattijs Korpershoek
5f7e01e9d5 usb: gadget: fastboot: detach usb on reboot commands
When host issues "fastboot reboot fastboot", it's expected that the
board drops the USB connection before resetting.

On some boards, such as Khadas VIM3L and SEI610, this is not the case.

We observe the following error:
$ fastboot reboot fastboot
Rebooting into fastboot                            OKAY [  0.004s]
fastboot: error: Failed to boot into userspace fastboot; one or more components might be unbootable.

This does not happen when we use the RST button on the board.
It can be reproduced in linux with:
  # echo b > /proc/sysrq-trigger

In this case, we hit a undefined hardware behavior, where D+ and D-
are in an unknown state. Therefore the host can't detect usb
disconnection.

Make sure we always call usb_gadget_release() when a "fastboot reboot"
command is issued.

Note: usb_gadget_release() should be called before g_dnl_unregister()
because g_dnl_unregister() triggers a complete() call on each
endpoint (thus calling do_reset()).

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2022-10-10 18:08:18 +02:00
Patrice Chotard
75341e9c16 usb: ehci: Remove unused ehci_{setup,shutdown}_phy() helpers
Remove unused ehci_{setup,shutdown}_phy() helpers now replaced by
generic_{setup,shutdown}_phy().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2022-10-10 18:08:18 +02:00
Patrice Chotard
083f8aa978 usb: ehci: Make usage of generic_{setup,shutdown}_phy() helpers
Replace ehci_setup_phy() and ehci_shutdown_phy () by respectively
generic_setup_phy() and generic_shutdown_phy().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2022-10-10 18:08:18 +02:00
Patrice Chotard
10005004db usb: ohci: Make usage of generic_{setup,shutdown}_phy() helpers
Replace ohci_setup_phy() and ohci_shutdown_phy () by respectively
generic_setup_phy() and generic_shutdown_phy().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2022-10-10 18:08:18 +02:00
Patrice Chotard
84e561407a phy: Add generic_{setup,shutdown}_phy() helpers
In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and
{ehci,ohci}_shutdown_phy() shares 95% of common code.
Factorize this code in new generic_{setup,shudown}_phy() functions.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2022-10-10 18:08:18 +02:00
Marek Vasut
7cc1af902d usb: gadget: Clean up Makefile ifdeffery
Take the USB_ETHER ifdef block apart and make use of obj-$(VAR) instead
to include the source files in build. The duplicate CI_UDC entry is now
removed, the USB_DEVICE ifdef is now reduced to core.o ep.o addition,
the ether.o can be conditionally compiled in using USB_ETHER.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-10 18:08:18 +02:00
Tom Rini
73e741b8ee Merge tag 'u-boot-nand-20221009' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next
- mtd: Update the function name to 'rfree'
 - Support NAND ONFI EDO mode for imx8mn architecture
 - dm: clk: add missing stub when CONFIG_CLK is deactivated
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Merge tag 'u-boot-nand-20221009' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash

- mtd: Update the function name to 'rfree'
- Support NAND ONFI EDO mode for imx8mn architecture
- dm: clk: add missing stub when CONFIG_CLK is deactivated
2022-10-10 08:17:08 -04:00
Alexander Dahl
63c46e028c fpga: virtex2: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-11-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
1fda847114 fpga: spartan3: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-10-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
bc33b69604 fpga: spartan2: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-9-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
40923f5611 fpga: ACEX1K: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-8-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
29e58112ed fpga: cyclon2: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-7-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
6c62e8ffd9 fpga: altera: Use logging feature instead of FPGA_DEBUG
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-6-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
27fb2e25e5 fpga: virtex2: Fix printf format string warnings
Warning appears if built with FPGA_DEBUG defined:

  CC      drivers/fpga/virtex2.o
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ssm_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:333:11: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
    PRINTF("%s:%d:done went active early, bytecount = %d\n",
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           __func__, __LINE__, bytecount);
                               ~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’
 #define PRINTF(fmt, args...) printf(fmt, ##args)
                                     ^~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ss_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:468:12: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
     PRINTF("%s:%d:done went active early, bytecount = %d\n",
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            __func__, __LINE__, bytecount);
                                ~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’
 #define PRINTF(fmt, args...) printf(fmt, ##args)
                                     ^~~

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-5-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
0ff33f464f fpga: spartan3: Fix printf arguments warning
The additional comma messes up the arguments.
Warning appears if built with FPGA_DEBUG defined:

      CC      drivers/fpga/spartan3.o
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’:
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:118:11: warning: too many arguments for format [-Wformat-extra-args]
       PRINTF ("%s: Function Table:\n"
               ^~~~~~~~~~~~~~~~~~~~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:18:37: note: in definition of macro ‘PRINTF’
     #define PRINTF(fmt,args...) printf (fmt ,##args)
                                         ^~~

Fixes: 875c78934e ("Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-4-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
cf4d6b519d fpga: spartan2: Fix printf arguments warning
That extra comma messes up format arguments.
Warning appears if built with FPGA_DEBUG defined:

      CC      drivers/fpga/spartan2.o
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c: In function ‘spartan2_sp_load’:
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:112:11: warning: too many arguments for format [-Wformat-extra-args]
       PRINTF ("%s: Function Table:\n"
               ^~~~~~~~~~~~~~~~~~~~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:12:37: note: in definition of macro ‘PRINTF’
     #define PRINTF(fmt,args...) printf (fmt ,##args)
                                         ^~~
      CC      drivers/fpga/spartan3.o
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’:
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:117:11: warning: too many arguments for format [-Wformat-extra-args]
       PRINTF ("%s: Function Table:\n"
               ^~~~~~~~~~~~~~~~~~~~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:17:37: note: in definition of macro ‘PRINTF’
     #define PRINTF(fmt,args...) printf (fmt ,##args)
                                         ^~~

Fixes: e221174377 ("Initial revision")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-3-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Alexander Dahl
312c4b1130 fpga: Add missing Kconfig symbols for old FPGA drivers
Those drivers could not be built anymore without those options present.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com
2022-10-10 12:28:08 +02:00
Venkatesh Yadav Abbarapu
673f18955e clk: versal: Mark versal_clock_setup() as static
Fix the following sparse and compile time warning
triggered with W=1:

drivers/clk/clk_versal.c:605:5:
warning: no previous prototype for 'versal_clock_setup'
[-Wmissing-prototypes]
605 | int versal_clock_setup(void)

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221007105535.31902-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-10 12:28:08 +02:00
Venkatesh Yadav Abbarapu
024cfd0ab5 soc: xilinx: zynqmp: Mark soc_xilinx_zynqmp_get_machine() as static
Fix the following sparse and compile time warning triggered with W=1:

drivers/soc/soc_xilinx_zynqmp.c:288:5:
warning: no previous prototype for 'soc_xilinx_zynqmp_get_machine'
[-Wmissing-prototypes]

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004055201.26146-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-10 12:28:08 +02:00
Michael Trimarchi
90cce0582d mtd: mxs_nand: Support EDO mode for imx8mn architecture
Add support for imx8mn architecture in order to run the NAND
in fast edo mode.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Dario Binacchi
6b7149a046 mtd: mxs_nand: get the clock with the right name
Rename the gpmi_apb_bch clock name to gpmi_bch_apb, as you can find in
the device tree.

Fixes: commit a59691280d ("MXS_NAND: Add clock support for iMX8")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Dario Binacchi
d5fb94ee96 mtd: mxs_nand: don't get the gpmi_apbh_dma clock
This clock name is not present in any U-boot and Linux kernel device
tree.

Fixes: commit a59691280d ("MXS_NAND: Add clock support for iMX8")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Michael Trimarchi
710c4ffb89 clk: imx: clk-imx8mn add gpmi nand clocks
Add gpmi nand clock. Those clock can be used in mxs nand driver
to run nand to EDO mode 5, 4, ...

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Michael Trimarchi
d2e82ad9e0 clk: imx: gate2 support shared counter and relative clock functions
Add shared counter in order to avoid to swich off clock that
are already used.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Roger Quadros
b6f9f98df6 mtd: nand: Fix SPL build after migration of CONFIG_SYS_NAND_SELF_INIT to Kconfig
This fixes the below build error if nand.c is included in
an SPL build.

/work/u-boot/drivers/mtd/nand/raw/nand.c: In function ‘nand_init_chip’:
/work/u-boot/drivers/mtd/nand/raw/nand.c:82:28: error: ‘nand_chip’ undeclared (first use in this function)
   82 |  struct nand_chip *nand = &nand_chip[i];
      |                            ^~~~~~~~~
/work/u-boot/drivers/mtd/nand/raw/nand.c:82:28: note: each undeclared identifier is reported only once for each function it appears in
/work/u-boot/drivers/mtd/nand/raw/nand.c:84:20: error: ‘base_address’ undeclared (first use in this function); did you mean ‘base_addr’?
   84 |  ulong base_addr = base_address[i];
      |                    ^~~~~~~~~~~~
      |                    base_addr

Fixes: 068c41f1cc ("Finish conversion CONFIG_SYS_NAND_SELF_INIT to Kconfig")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-08 10:53:13 +02:00
Tom Rini
11ef7f07ce Pull request for efi-2023-01-rc1
UEFI:
 
 * Provide driver binding protocol to registered events for block devices
 * Code simplification and refactoring
 * Fix pylint errors in test_efi_secboot
 
 Other:
 
 * Improve checks for register ranges
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Merge tag 'efi-2023-01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc1

UEFI:

* Provide driver binding protocol to registered events for block devices
* Code simplification and refactoring
* Fix pylint errors in test_efi_secboot

Other:

* Improve checks for register ranges
2022-10-07 11:51:05 -04:00
Venkatesh Yadav Abbarapu
b451330df2 spi: zynqmp_qspi: Mark zynqmp_qspi_set_tapdelay() as static
Fix the following sparse and compile time warning triggered with W=1:

drivers/spi/zynqmp_gqspi.c:286:6:
warning: no previous prototype for 'zynqmp_qspi_set_tapdelay'
[-Wmissing-prototypes]

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004053730.25602-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-07 11:31:27 +02:00
Jim Liu
2a6218369c clk: nuvoton: Add support for NPCM845
Add clock controller driver for NPCM845

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
2022-10-06 21:05:17 -04:00
Ravi Gunasekaran
d0fc818259 net: ti: am65-cpsw-nuss: Enable MDIO manual mode
For the TI SoCs affected by errata i2329, enable MDIO manual
mode by default

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-06 21:05:17 -04:00
Ravi Gunasekaran
9ea30ea66a net: ti: cpsw-mdio: Add workaround for errata i2329
In certain TI SoCs, on the CPSW and ICSS peripherals, there is
a possibility that the MDIO interface returns corrupt data on
MDIO reads or writes incorrect data on MDIO writes. There is also
a possibility for the MDIO interface to become unavailable until
the next peripheral reset.

The workaround is to configure the MDIO in manual mode and disable the
MDIO state machine and emulate the MDIO protocol by reading and writing
appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
to manipulate the MDIO clock and data pins.

More details about the errata i2329 and the workaround is available in:
https://www.ti.com/lit/er/sprz487a/sprz487a.pdf

Add implementation to disable MDIO state machine, configure MDIO in manual
mode and provide software MDIO read and writes via MDIO bitbanging. Allow
the MDIO to be initialized based on the need for manual mode.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-06 21:05:17 -04:00
Dhruva Gole
742f302cdc dma: ti: k3-udma: Fix 'SZ_64K’ undeclared error
Include linux/sizes.h because it defines SZ_64K which is used in many
places inside k3-udma.c
This fixes the error: ‘SZ_64K’ undeclared which appears during build
time

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-10-06 21:05:17 -04:00
Sergei Antonov
d100d3e18e gpio: ftgpio010: Add support for Faraday Technology FTGPIO010
Add Faraday Technology's FTGPIO010 controller driver.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
2022-10-06 21:05:17 -04:00
Heinrich Schuchardt
947d4f132b regmap: fix range checks
On the 32bit ARM sandbox 'dm ut dm_test_devm_regmap' fails with an abort.
This is due to incorrect range checks.

On 32-bit systems the size of size_t and int is both 32 bit. The expression
(offset + val_len) is bound to overflow if offset == -1. Add an overflow
check.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-06 22:54:56 +02:00
Stefan Roese
37bb396669 timer: orion-timer: Only init timer once
Move the code making sure that the timer is initialized only once into
orion_timer_init(), which is called from timer_early_init() and from
orion_timer_probe(). This way the timer is not re-initialized.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
2022-10-06 10:15:35 +02:00
Chris Packham
1ba0018218 mtd: nand: pxa3xx: simplify ECC hardware parameters
Replace the if/else chain in pxa_ecc_init() with a lookup table. This
makes the code more concise and hopefully easier to follow. Remove the
unused ecc_layout tables and replace it with a single dummy one (the
pxa3xx driver has never used this but the mtd subsystem expects it to be
provided).

Tested on an Allied Telesis x530 switch with Micron MT29F2G08ABAEAWP
NAND Flash.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-10-06 10:15:34 +02:00
Ashok Reddy Soma
aba0e6510f mmc: zynq_sdhci: Read power-domains id from DT and use
Firmware calls need node_id which is basically "power-domains" id.
At present static values are used based on the "device_id" property of
dt.
Instead of this, read "power-domains" id from dt and use it. Add a
element called node_id in priv structure and read it from dt. Replace
static node_id with this priv->node_id across the driver.

Since "device_id" is not used anywhere else simply remove it.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Ashok Reddy Soma
cbdee4d5e8 mmc: zynq_sdhci: Change node_id prototype to u32
In Versal platform power domain node_id is bigger than u8, hence
change prototype to u32 to accommodate. Change u8 to u32 in the function
prototypes that use node_id and remove casting to u32 from
xilinx_pm_request() call parameters.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Venkatesh Yadav Abbarapu
9a082d2548 net: Fix static checker warnings
Here are the smatch warning messages:

drivers/net/xilinx_axi_emac.c:324 axiemac_phy_init()
error: 'phydev' dereferencing possible ERR_PTR()

drivers/net/zynq_gem.c:340 zynq_phy_init()
error: 'priv->phydev' dereferencing possible ERR_PTR()

Fix by adding error checking before dereferencing the pointer.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20220929045605.23964-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Samuel Obuch
f4cf004d27 net: emaclite: fix handling for IP packets with specific lengths
The maximum length is capped similarly to the emaclite_send function.
Avoid integer underflow for values of ip->ip_len < 30, the minimum
length of an IP packet is 21 bytes.

Signed-off-by: Samuel Obuch <samuel.obuch@codasip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/20220927112103.155689-3-samuel.obuch@codasip.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Samuel Obuch
3d1700296c net: emaclite: fix xemaclite_alignedread/write functions
Use __raw_read* and __raw_write* functions to ensure read/write
is passed to the memory-mapped regions, as non-volatile accesses
may get optimised out.

Signed-off-by: Samuel Obuch <samuel.obuch@codasip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/20220927112103.155689-2-samuel.obuch@codasip.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Samuel Obuch
078d8eb5bb net: emaclite: enable for more architectures
Function ioremap_nocache seems to be defined only for MIPS and Microblaze
architectures. Therefore, the function call in the emaclite driver causes
this driver to be unusable with other architectures, for example RISC-V.

Use ioremap function instead of ioremap_nocache, and include linux/io.h
instead of asm/io.h, so that ioremap function is automatically created,
if not defined by the architecture. We can switch to the ioremap function,
as Microblaze's ioremap_nocache is just empty and in MIPS implementations
of ioremap_nocache and ioremap are the same.

Signed-off-by: Samuel Obuch <samuel.obuch@codasip.com>
Link: https://lore.kernel.org/r/20220927112103.155689-1-samuel.obuch@codasip.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Ashok Reddy Soma
ef2896a4d2 firmware: zynqmp: Change loadable config object from APU_0 to OCM_BANK_0
To check dynamic loading of config object, currently APU_0 is used.
Suggestion from pmwfw team is to load OCM_BANK_0 and check for
XST_PM_NO_ACCESS error only to skip future config objects. Other errors
should not be considered for skipping. Change from NODE_APU_0 to
NODE_OCM_BANK_0 and check for XST_PM_NO_ACCESS to skip future config
objects.

Add ":  " to printf statement when there is no permission to load config
object, to align with PMUFW version print.

Update kernel doc for return value for zynqmp_pmufw_load_config_object().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2784018844ba4afced0e3edff76bdbfe532f517d.1664523444.git.michal.simek@amd.com
2022-10-05 11:36:54 +02:00
Alexander Dahl
1323d08bdf dm: fpga: Introduce new uclass
For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.

Suggested-by: Michal Simek <michal.simek@amd.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Dahl <post@lespocky.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 08:43:53 +02:00
Tom Rini
2d45913534 Merge branch 'next' 2022-10-03 15:39:46 -04:00
Simon Glass
db1ef1e12b dm: core: Support copying properties with ofnode
Add a function to copy properties from one node to another.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
0b58eaa89c dm: core: Allow copying ofnode property data when writing
At present ofnode_write_prop() is inconsistent between livetree and
flattree, in that livetree requires the caller to ensure the property
value is stable (e.g. in rodata or allocated) but flattree does not, since
it makes a copy.

This makes the API call a bit painful to use, since the caller must do
different things depending on OF_LIVE.

Add a new 'copy' argument which tells the function to make a copy if
needed. Add some tests to cover this behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
5e96925ba5 dm: core: Complete phandle implementation using the other FDT
We need to be able to look up phandles in any FDT, not just the control
FDT. Use the 'other' FDT to test this, with a helper function which gets
this as an oftree that can then we used as needed.

Add a few more tests and some comments at the top of the file, to explain
what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
92291652b5 dm: core: Add the ofnode multi-tree implementation
Add the logic to redirect requests for the device tree through a function
which can look up the tree ID. This works by using the top bits of
ofnode.of_offset to encode a tree.

It is assumed that there will only be a few device trees used at runtime,
typically the control FDT (always tree ID 0) and possibly a separate FDT
to be passed the OS.

The maximum number of device trees supported at runtime is 8, with this
implementation. That would use bits 30:28 of the node-offset value,
meaning that the positive offset range is limited to bits 27:0, versus
30:1 with this feature disabled. That still allows a device tree of up
to 256MB, which should be enough for most FITs. Larger ones can be
supported by using external data with the FIT, or by enabling OF_LIVE.

Update the documentation a little and fix up the comment for
ofnode_valid().

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
41b65d68ec dm: core: Add definitions for multiple ofnode trees
At present, unless OF_LIVE is enabled, ofnode only supports access to one
device tree, the control FDT. This is because only the node offset is
encoded in ofnode, with the tree being implicit.

This makes ofnode (without OF_LIVE) unsuitable for device tree fixups, as
implemented by ft_board_setup() and other such functions.

To solve this, we can use the top bits of the node offset to hold a tree
ID.

Add the definitions for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
b7bd94f1a8 dm: core: Split ofnode_path_root() into two functions
This function turns out to be a little confusing since it looks up a path
and also registers the tree. Split it into two, one that gets the root
node and one that looks up a path, so the purpose is clear.

Registering the tree will happen in a function to be added in a later
patch, called oftree_from_fdt().

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
2187cb7e4a dm: core: Allow obtaining a node offset in the same tree
In some cases we want to obtain an ofnode in the same tree as a different
ofnode, such as when looking up a subnode. At present this is trivial,
since there is only one tree. When there are multiple trees, this
implementation will change.

Also move the ofnode_to_offset() function up higher in the header file,
since we will need to provide a different implementation with multiple
trees.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
928d267aee dm: core: Add a way to look up a phandle in an oftree
When we have multiple trees, the ofnode logic needs to be told which one
to use. Create a new function which takes an oftree argument, along with
a helper to obtain the FDT pointer from an oftree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
a3f50d0386 dm: core: Add an ofnode function to obtain the flat tree
The flat device tree is assumed to be the control FDT but this is not
always the case. Update the ofnode implementation to obtain the node via
an function call so we can eventually add support for selecting different
trees.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:43 -04:00
Simon Glass
66d0d0c188 dm: core: Expand integer-reading tests
The current tests do not cover all the behaviour. Add some more.

Tidy up a few inconsistencies between livetree and flattree which come to
light with these tests. Also drop the -ENODATA error since it is never
actually returned.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 22:43:42 -04:00
Simon Glass
8909066199 dm: core: Drop ofnode_is_available()
This function is also available as ofnode_is_enabled(), so use that
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:31 -04:00
Simon Glass
f46ec93ed5 dm: core: Avoid creating a name property when unflattening
The current implementation creates a 'name' value for every node. This
is not needed for the latest device tree format, which includes a name in
the node header.

Adjust the code to point the name at the node header instead.

Also simplify ofnode_get_name(), now that we can rely on it to set the
name correctly. Update the comment to make it clear what name the root
node has.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:14 -04:00
Simon Glass
9243224687 dm: core: Rename ofnode_get_property_by_prop()
The current name is quite unwieldy. Change it to use an ofprop_ prefix
and shorten it. Fix the return-value comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:14 -04:00
Simon Glass
4b1f571465 dm: core: Rename ofnode_get_first/next_property()
Drop the 'get' in these names since it does not fit with the rest of
the API.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:14 -04:00
Simon Glass
1701359f75 dm: core: Reduce code size with dev_of_offset()
Update the function to mark it with the const attribute. Also avoid
calling it multiple times in the devfdt_get_addr_index() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:14 -04:00
Simon Glass
9830698765 dm: core: Drop the const from ofnode
Now that we support writing to ofnodes, the const is not accurate. Drop
it to avoid undesirable casting.

Also drop the ofnode_to_npw() which is now the same as ofnode_to_np().

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
c3a194dec9 dm: core: Support writing a property to an empty node
At present this does not work with livetree. Fix it and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
ffe9039249 dm: core: Allow adding ofnode subnodes
Add this feature to the ofnode interface, supporting both livetree and
flattree. If the node exists it is returned, along with a -EEXIST error.
Update the functions it calls to handle this too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
829d51246f dm: core: Pass a root node to of_find_node_by_phandle()
This function currently assumes that the control FDT is used. Update it
to allow a root node to be passed, so it can work with any tree.

Also add a comment to ofnode_get_by_phandle() so that its purpose is
clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
96d0c4514f sandbox: power: Update PMIC driver to use log
Use the log functions instead of pr_...() so we can avoid using __func__.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-09-29 16:07:57 -04:00
Simon Glass
f3543e6944 treewide: Drop image_header_t typedef
This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Pali Rohár
c5f5ee3732 watchdog: max6370: use __udelay() to avoid recursion
The udelay() function in lib/time.c contains a WATCHDOG_RESET()
call. So use __udelay() in max6370_wdt.c to prevent recursion.

Fixes: 0a095fc53b ("watchdog: Add MAX6370 watchdog timer driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-27 12:25:51 +02:00
Rasmus Villemoes
51443c9a49 watchdog: gpio_wdt: use __udelay() to avoid recursion
The udelay() function in lib/time.c contains a WATCHDOG_RESET()
call. The only reason this doesn't lead to a catastrophic infinite
recursion is due to the rate-limiting in wdt-uclass.c:

		if (time_after_eq(now, priv->next_reset)) {
			priv->next_reset = now + priv->reset_period;
			wdt_reset(dev);
		}

But this would fall apart if ->next_reset was updated after calling the
device's reset method.

This is needlessly fragile, and it's easy enough to avoid that
recursion in the first place by just using __udelay() directly.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-27 12:25:40 +02:00
Tom Rini
55ccdee315 Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
 - Add support for new Versal NET SOC
 
 zynqmp:
 - Use mdio bus for ethernet phy description
 - Wire ethernet phy reset via i2c-gpio
 
 versal:
 - Config cleanup
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Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.01-rc1 (round 2)

xilinx:
- Add support for new Versal NET SOC

zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio

versal:
- Config cleanup
2022-09-26 11:28:14 -04:00
Tom Rini
ffa2c88bcf Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next 2022-09-26 11:27:30 -04:00
Tom Rini
f117c54cc8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- gpio: turris_omnia_mcu: Fix registering gpios (Pali)
2022-09-26 08:30:17 -04:00
Jay Buddhabhatti
a41c33992a reset: zynqmp: Enable reset driver for Versal NET
Enable zynqmp reset driver for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
b6b2ad1cea mailbox: zynqmp: Enable ipi mailbox driver for Versal NET
Enable mailbox configs for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b3a9a6a58b74d17e2ec5f60617fa42062fbab951.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
2a00cef820 firmware: zynqmp: Add Versal NET compatible string
Add compatible string for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ec73f786e1c89094752ff3693f6f0fb4536c85c5.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
ff33227819 clk: versal: Enable clock driver for Versal NET
Add support for Versal NET compatible string in clock driver.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Michal Simek
2389647225 spi: zynqmp_gqspi: Add support for Versal NET
Add support for Versal NET platform.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f374e9a81f2d85de1240029f3ba5f6423cfa0680.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Michal Simek
1e681448a3 spi: cadence_qspi: Add support for Versal NET platform
Trivial changes to support cadence ospi driver for Versal NET platform.
Also avoid ospi flash reset for now.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Pali Rohár
54bcd84adf gpio: turris_omnia_mcu: Fix registering gpios
Currently all GPIOs supported by CMD_EXT_CONTROL/CMD_GET_EXT_CONTROL_STATUS
commands (last 16 GPIOs) are available only when FEAT_PERIPH_MCU feature
bit is set. So do not register these GPIOs by U-Boot driver when this
feature bit is not set, so U-Boot 'gpio' command would see only GPIOs which
really exists.

Fixes: 5e4d24ccc1 ("gpio: Add Turris Omnia MCU driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-26 10:04:37 +02:00
Alison Huffman
206af3dec0 Fix out of bound access of ep array.
When processing USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE, and
USB_REQ_GET_STATUS packets in dwc2_ep0_setup an out of bounds access
can occur. This is caused by the wIndex field of the usb control packet
being used as an index into an array whose size is DWC2_MAX_ENDPOINTS (4).

Signed-off-by: Alison Huffman <alisn@google.com>
2022-09-26 01:49:36 +02:00
Jim Liu
693765a720 usb: host: nuvoton: Add nuvoton NPCM7xx ehci/ohci driver
Add nuvoton BMC NPCM750 ehci/ohci driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-09-26 01:49:36 +02:00
Simon Glass
46df024394 sandbox: Convert to use driver model for SCSI
At present sandbox is producing a warning about SCSI migration. Drop the
legacy code and replace it with a new implementation.

Also drop the SATA command, which does not work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 13:59:50 -06:00
Simon Glass
02cea1145a sandbox: scsi: Move request-handling code to scsi_emul
Move this code into the emulator file so it can be used by multiple
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 13:59:38 -06:00
Simon Glass
1ac42900d8 sandbox: scsi: Move structs to header file
Move these to the SCSI header file so we can access them from multiple
emulators.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
e074df4d23 sandbox: scsi: Remove setup calls from handle_read()
Move the device-specific code out into the top-level function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
f75b6f76a4 sandbox: scsi: Move reply setup out of helper
Move this code out of the helper function so we can (later) add it as part
of the shared emulation code. Set a default value of 0 for buff_used since
that is what we use when there is an error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
f148ad1b5f sandbox: scsi: Move file size into shared struct
Move this information into struct scsi_emul_info so we can use it in
common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
a3718f1e53 sandbox: scsi: Move block size into shared struct
Move this information into struct scsi_emul_info so we can use it in
common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
0c12d9dd23 scsi: Move vendor/product info into the shared struct
Move this information into struct scsi_emul_info so we can use it in
common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
fc7a7ed3a6 sandbox: Move buffer to scsi_emul_info
Move the buffer into this struct so it can be shared between different
implementations.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
1377d448a2 scsi: Move core emulation state into a new struct
In preparation for sharing the emulation code between two drivers, move
some of the fields into a new struct. Use a separate header file so it
can be used by various drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
0e0b9e9459 scsi: Move cmd_phase enum to the header
This can be used by common files, so move it to the SCSI header and rename
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
8bae79744b sandbox: usb: Rename transfer_len in protocol struct
This has the same name as a field in our local private struct, which is
confusing. Change the name to xfer_len instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Simon Glass
8149b1500d blk: Rename if_type to uclass_id
Use the word 'uclass' instead of 'if_type' to complete the conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25 08:30:05 -06:00
Pali Rohár
989cc40f80 serial: Call flush() before changing baudrate
Changing baudrate is a sensitive operation. To ensure that U-Boot messages
printed before changing baudrate are not lost, call new U-Boot console
flush() function.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24 11:34:38 -04:00
Pali Rohár
78b5243182 serial: Implement serial_flush() function for console flush() fallback
Like in all other console functions, implement also serial_flush() function
as a fallback int console flush() function.

Flush support is available only when config option CONSOLE_FLUSH_SUPPORT is
enabled. So when it is disabled then provides just empty static inline
function serial_flush().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24 11:34:37 -04:00
Pali Rohár
016e2be96d serial: Implement flush callback
UART drivers have putc/puts functions which just put characters into HW
transmit queue and do not wait until all data are transmitted.

Implement flush callback via serial driver's pending(false) callback which
waits until HW transmit all characters from the queue.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24 10:47:01 -04:00
Pali Rohár
a86e294f9f ddr: fsl: Fix re-align of verbose DRAM information for non-SPL builds
During init_dram() is called also compute_lowest_common_dimm_parameters()
function which prints multi-line detailed output. So print also re-aligning
filler after "Detected ?DIMM" line to have "DRAM:  " output aligned.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
2721997654 ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit mode
U-Boot core code already handles the case when RAM size is bigger than
CONFIG_MAX_MEM_MAPPED. So there is no need to do duplicate check in fsl ddr
driver for CONFIG_MAX_MEM_MAPPED. Instead simplify code to just check if
RAM size can be representable in phys_size_t type. And avoid printing
warning if phys_size_t is just 1 byte smaller than RAM size, which is the
typical situation with 4 GB DDR module.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
922460be0b ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_t
Function fsl_ddr_compute() always return size in unsigned long long type,
but function fsl_ddr_sdram_size() returns size in phys_size_t type.

When 36-bit addressing mode is not enabled then phys_size_t type is only
32-bit and thus it cannot store value 4GB (0x100000000). Function
fsl_ddr_sdram_size() in this case returns truncated value 0x0.

Fix this issue by returning the highest representable value, which is
0xffffffff (4GB - 1 byte).

This change fixes crashing of proper U-Boot because it detected 4 GB module
as RAM with zero size.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
cf4eba4eb6 ddr: fsl: Fix checking for maximal mappable memory
Check needs to be done against CONFIG_MAX_MEM_MAPPED macro and not fixed
size 4GB (as CONFIG_MAX_MEM_MAPPED can be lower and for example for e500
cores it is just 2GB). Also fix printf re-align, which should be applied
only for non-SPL builds, during init_dram() call.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Weijie Gao
6136a23263 cpu: add basic cpu driver for MediaTek ARM chips
Add basic CPU driver used to retrieve CPU model information.

Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23 15:09:16 -04:00
Weijie Gao
40746bf429 clk: mediatek: add clock driver support for MediaTek MT7981 SoC
This patch adds clock driver support for MediaTek MT7981 SoC

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
37d5a9a29d clk: mediatek: add clock driver support for MediaTek MT7986 SoC
This patch adds clock driver support for MediaTek MT7986 SoC

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
ad832b915a clk: mediatek: add CLK_XTAL support for clock driver
This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
570b0840b1 clk: mediatek: add infrasys clock mux support
This patch adds infrasys clock mux support for mediatek clock drivers.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
98a8bbb9ea clk: mediatek: add support to configure clock driver parent
This patch adds support for a clock node to configure its parent clock
where possible.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
7fb33e9aea clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock
The mtk clock framework in u-boot uses array index for searching clock
parent (kernel uses strings for search), so we need to specify a special
clock with ID=0 for CLK_XTAL in u-boot.

In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
expected.

However for newer chips, they may have some clocks with ID=0 not
representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
called. Current logic will make entire clock driver not working.

This patch adds a flag to indicate that whether a clock driver needs clocks
with ID=0 to call mtk_topckgen_get_mux_rate.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Weijie Gao
59acdf8afe pinctrl: mediatek: add pinctrl driver for MT7986 SoC
This patch adds pinctrl and gpio support for MT7986 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
ace67d1097 pinctrl: mediatek: add pinctrl driver for MT7981 SoC
This patch adds pinctrl and gpio support for MT7981 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
9ad71f6340 i2c: add support for MediaTek I2C interface
This patch adds support for MediaTek I2C interface

Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
b34a2368d6 spi: add support for MediaTek spi-mem controller
This patch adds support for spi-mem controller found on newer MediaTek SoCs
This controller supports Single/Dual/Quad SPI mode.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2022-09-23 15:09:15 -04:00