Commit graph

2 commits

Author SHA1 Message Date
Sebastian Reichel
717bf50f4b board: ge: bx50v3: cleanup phy config
The current PHY rework does the following things:

1. Configure 125MHz clock
2. Setup the TX clock delay (RX is enabled by default),
3. Setup reserved bits to avoid voltage peak

The clock delays are nowadays already configured by the
PHY driver (in ar803x_delay_config). The code for that
can simply be dropped. The clock speed can also be
configured by the PHY driver by adding the device tree
property "qca,clk-out-frequency".

What is left is setting up the undocumented reserved bits
to avoid the voltage peak problem. I slightly improved its
documentation while updating the board's PHY rework code.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-12-26 14:56:09 +01:00
Robert Beckett
8c26739859 board: ge: bx50v3: sync devicetrees from Linux
Copy device trees from linux, keeping them as separate files for
each board to ease future sync.

Update board code to use generic bx50v3 dt initially, then select
the specific dt based on board detection.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-07 10:26:56 +01:00