Commit graph

7120 commits

Author SHA1 Message Date
Mugunthan V N
6463170064 net: phy: dp83867: Add support for MAC impedance configuration
Add support for programmable MAC impedance configuration and
fix typo in DT impedance parameters names.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Tom Rini
c83a824e62 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/ls1046aqds_defconfig
	configs/ls1046aqds_nand_defconfig
	configs/ls1046aqds_qspi_defconfig
	configs/ls1046aqds_sdcard_ifc_defconfig
	configs/ls1046aqds_sdcard_qspi_defconfig
	configs/ls1046ardb_emmc_defconfig
	configs/ls1046ardb_qspi_defconfig
	configs/ls1046ardb_sdcard_defconfig
2017-02-03 20:33:42 -05:00
Prabhakar Kushwaha
8e63ed518d arch: arm: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.

Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:31:19 -08:00
Prabhakar Kushwaha
7d559604d0 board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:30:28 -08:00
Tom Rini
43ade93bdb Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-02-01 16:34:25 -05:00
Tom Rini
f77309d343 Merge git://www.denx.de/git/u-boot-marvell 2017-02-01 06:57:35 -05:00
Mario Six
a1b6b0a9c1 arm: mvebu: Implement secure boot
The patch implements secure booting for the mvebu architecture.

This includes:
- The addition of secure headers and all needed signatures and keys in
  mkimage
- Commands capable of writing the board's efuses to both write the
  needed cryptographic data and enable the secure booting mechanism
- The creation of convenience text files containing the necessary
  commands to write the efuses

The KAK and CSK keys are expected to reside in the files kwb_kak.key and
kwb_csk.key (OpenSSL 2048 bit private keys) in the top-level directory.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:04:18 +01:00
Reinhard Pfau
3add68c996 arm: mvebu: spl.c: Remove useless gd declaration
ddaa905 ("arm: mvebu: Add DM (driver model) support") removed the
assignment of the gd pointer, but kept the (now superfluous) declaration
of the gd pointer.

Remove this declaration.

Signed-off-by: Reinhard Pfau <pfau@gdsys.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:02:49 +01:00
Mario Six
2ad4309441 mvebu: Add board_pex_config()
Allow boards to do some initialization when PCIe comes up.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:02:14 +01:00
Dirk Eibach
882d3fa6dd pci: mvebu: Fix Armada 38x support
Armada 38x has four PCI ports, not three.

The optimization in pci_init_board() seems to assume that every port has
three lanes. This is obviously wrong, and breaks support for Armada 38x.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:01:19 +01:00
York Sun
0ae7050c25 armv8: ls1046a: Enable workaround for erratum A-008336
Erratum A-008336 applies to LS1046A per latest SoC document.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-01-31 09:25:22 -08:00
Masahiro Yamada
08aa0334c6 mmc: zynq: rename CONFIG_ZYNQ_SDHCI to CONFIG_MMC_SDHCI_ZYNQ
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.

While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-31 21:50:47 +09:00
Lukasz Majewski
11bd5e7b62 BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board
This patch provides u-boot support for Liebherr (LWN) mccmon6 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-30 16:24:47 +01:00
Patrick Bruenn
355ed4b431 arm: dts: imx53-cx9020: fix packetloss on fec_mxc
The pinmuxing for i.MX53 FEC ethernet copied from
<kernel>/arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9)
was bad. It is different from the manual pinmuxing in
<u-boot>/board/freescale/mx53loco/mx53loco.c which was used in
cx9020 implementation previously before mainlining into u-boot.
It seems the bug in imx53-qsb kernel device tree is hidden for so long,
because it was never used, by the kernel driver.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2017-01-30 16:24:19 +01:00
Masahiro Yamada
9c572684b4 ARM: uniphier: compile board data only for SPL
Now U-Boot proper need not get the uniphier_boards array.  Compile
it only for SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
513cfaccc8 ARM: uniphier: refactor cmd_ddrmphy
Make it look like cmd_ddrphy.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
fada9eafe1 ARM: uniphier: clean up UMC init for PXs2 SoC
Just cosmetic changes:
  - Rename prefix DMPHY_ to MPHY_ for consistency
  - Move UMC parameters below for complete decouple of PHY and UMC
  - Remove redundant whitespaces

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
bf52091786 ARM: uniphier: refactor cmd_ddrphy
It seems more readable to use arrays to get SoC specific parameters
instead of the crappy switch statement.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
c995f3a3c5 ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC
For LD20 SoC, the last 64 byte of each DRAM bank is used for the
dynamic training of DRAM PHY.  The regions must be reserved in DT to
prevent the kernel from using them.  Now gd->bd->bi_dram reflects
the actual memory banks.  Just use it instead of getting access to
the board parameters.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
3e9952be23 ARM: uniphier: detect RAM size by decoding HW register instead of DT
U-Boot needs to set up available memory area(s) in dram_init() and
dram_init_banksize().  It is platform-dependent how to detect the
memory banks.  Currently, UniPhier adopts the memory banks _alleged_
by DT.  This is based on the assumption that users bind a correct DT
in their build process.

Come to think of it, the DRAM controller has already been set up
before U-Boot is entered (because U-Boot runs on DRAM).  So, the
DRAM controller setup register seems a more reliable source of any
information about DRAM stuff.  The DRAM banks are initialized by
preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever),
so this means the source of the reliability is shifted from Device
Tree to such early-stage firmware.  However, if the DRAM controller
is wrongly configured, the system will crash.  If your system is
running, the DRAM setup register is very likely to provide the
correct DRAM mapping.

Decode the SG_MEMCONF register to get the available DRAM banks.
The dram_init() and dram_init_banksize() need similar decoding.
It would be nice if dram_init_banksize() could reuse the outcome
of dram_init(), but global variables are unavailable at this stage
because the .bss section is available only after the relocation.
As a result, SG_MEMCONF must be checked twice, but a new helper
uniphier_memconf_decode() will help to avoid code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Masahiro Yamada
773f5f63dc ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoC
The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB
memory footprint, which is significant in SPL.

There are PHY parameters for 5 boards, but they are actually not
board specific, but SoC specific.  After all, we just need to have
2 patterns, for LD20 and LD21.  Also, the shift values are small
enough to become "short" type instead of "int".  This change will
save about 3 KB memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-29 20:59:08 +09:00
Michael Kurz
d4363baada ARM: SPI: stm32: add stm32f746 qspi driver
This patch adds support for the QSPI IP found in stm32f7 devices.

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
2017-01-28 14:04:50 -05:00
Michael Kurz
b20b70fcc0 net: stm32: add designware mac glue code for stm32
This patch adds glue code required for enabling the designware
mac on stm32f7 devices.

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-28 14:04:47 -05:00
Michael Kurz
081de09d49 ARM: stm32: use clock setup function defined in clock.c
Use the clock setup function defined in clock.c instead of setting the
clock bits directly in the drivers.
Remove register definitions of RCC in rcc.h as these are already
defined in the struct in stm32.h

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-01-28 14:04:45 -05:00
Michael Kurz
dd3f0ebfb7 ARM: stm32: fix stm32f7 sdram fmc base address
The fmc base address is defined twice, once in fmc.h and once in stm32.h.
Fix wrong definition in stm32.h.
Remove the definiton in fmc.h.

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
2017-01-28 14:04:44 -05:00
Michael Kurz
bad5188be2 ARM: stm32: cleanup stm32f7 files
Cleanup stm32f7 files:
- use BIT macro
- use GENMASK macro
- use rcc struct instead of macro additions

Add missing stm32f7 register in rcc struct

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
2017-01-28 14:04:43 -05:00
Michael Kurz
b1a8de7e07 ARM: DTS: stm32: add stm32f746-disco device tree files
This patch adds the DTS source files needed for stm32f746-disco board
The files are based on the stm32f429/469 files from current linux
kernel.

Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi"

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-01-28 14:04:42 -05:00
Adam Ford
7f668a6fbe arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703
The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but
anything else is lumped into 36XX/37XX with an assumed 1GHz speed.

Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ).
This also adds the ability to distinguish between the DM3730, DM3725,
AM3715, and AM3703 and correctly display their maximum speed.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
2017-01-28 14:04:40 -05:00
Ladislav Michl
d5c9d4fbf0 arm: omap3: Fix cpuinfo frequency spelling
Frequency is measured in Hz.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
2017-01-28 14:04:39 -05:00
Masahiro Yamada
65f3219661 arm64: spin-table: add more information in Kconfig help
This feature seems to be sometimes misunderstood.  The intention is:

[1] Bring the slaves into the U-Boot proper image, not SPL (unless
    you have a special reason to do otherwise).

[2] The operation must be done in a board (SoC) specific manner
    since how to wake the slaves from the Boot ROM is SoC specific.

[3] The slaves must enter U-Boot proper after U-Boot relocates
    itself because the "cpu-release-addr" property points to the
    relocated memory area.

[2] is already explained in the help.  We can make [1] even clearer
by mentioning "U-Boot proper" instead of "U-Boot".  [3] is missing,
so I am adding it to the list.  Instead, "before the master CPU
jumps to the kernel" is a matter of course, so removed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-28 14:04:38 -05:00
Marcin Niestroj
ab38bf6a39 board/chiliboard: Add support for chiliBoard
chiliBoard is a development board which uses chiliSOM as its base.

Hardware specification:
 * chiliSOM (TI AM335x, DRAM, NAND)
 * Ethernet PHY (id 0)
 * USB host (usb1)
 * MicroSD slot (mmc0)

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-28 14:04:37 -05:00
Marcin Niestroj
a73c8b32a7 ARM: am335x: Add support for chiliSOM
chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/).
It can't exists on its own, but will be used as part of other boards.

Hardware specification:
 * TI AM335x processor
 * 128M, 256M or 512M DDR3 memory
 * up to 256M NAND

We place source inside arch/arm/mach-omap2/ directory and make it
possible to reuse initialization code (i.e. DDR, NAND init) for all
boards that use it.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-28 14:04:36 -05:00
maxims@google.com
d9b88d2547 aspeed: Support for ast2500 Eval Board
ast2500 Eval Board device tree and board specific configuration.
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28 14:04:33 -05:00
maxims@google.com
f6a6a9f049 aspeed: Board init functions and common configs for ast2500 based boards
Add configuration file with parameters that are very likely to be shared by
all ast2500-based boards.
Add ast2500-board.c file with the init code that is very likely to be
shared by all ast2500-based boards.
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28 14:04:32 -05:00
maxims@google.com
14e4b14979 aspeed: Add basic ast2500-specific drivers and configuration
Clock Driver

This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.

SDRAM MC driver

The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.

The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28 14:04:29 -05:00
maxims@google.com
4697abea62 aspeed: Add drivers common to all Aspeed SoCs
Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.

Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.

Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28 14:04:27 -05:00
Tom Rini
539cb8038e arm: Re-sync with full list of MACH_TYPE_xxx values
This re-syncs us with the official and full list of MACH_TYPE_xxx values
from http://www.armlinux.org.uk/developer/machines/

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-28 14:04:20 -05:00
Patrick Delaunay
b0cf733933 disk: convert CONFIG_DOS_PARTITION to Kconfig
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
2017-01-28 08:47:34 -05:00
Tang Yuantian
272a24fe8d armv8: ls1046a: added usb nodes in dts
The LS1046A processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-27 12:47:10 -08:00
Peng Fan
caf2578f65 imx: dts: mx6sxsabreauto: enable i2c2/3
Enable i2c2/3, add pinctrl settings.
Add max7310 for i2c3.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-01-27 10:53:05 +01:00
Peng Fan
6301e6570b imx: mx6sx: add dts for mx6sxsabreauto board
Add dts for mx6sxsabreauto board.
dts related files imported fro Linux (commit e5517c2a5a4).

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-01-27 10:52:10 +01:00
Marcin Niestroj
d4b1b52737 ARM: imx6ul: Move liteSOM source to SoC directory
Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested
in [1] during discussion of chiliSOM support patches.

[1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-27 10:48:07 +01:00
Stefan Agner
ac0a93fd21 imx_common: check for bmode Serial Downloader
Before commit 81c4eccb55 ("imx: mx6: fix USB bmode to use
reserved value") a non-reserved value has been used to trigger
Serial Downloader using bmode, which translated to a GPR9 value
of 0x10. However, on some boards the non-reserved value lead to
unreliable bmode command. With the above mentioned commit, U-boot
switched to use [7:4] b0001, which translates to GPR9 0x10 for
Serial Downloader mode. Check for the new value and classify it
as Serial Downloader mode.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Fabio Estevam <Fabio.Estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
2017-01-27 10:40:16 +01:00
Tom Rini
cf4128e53c Merge git://www.denx.de/git/u-boot-marvell 2017-01-26 12:26:24 -05:00
Simon Glass
4585601ae2 Convert CONFIG_ARCH_MISC_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_MISC_INIT

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:41 -05:00
Simon Glass
a5d67547dd Convert CONFIG_BOARD_EARLY_INIT_F to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_EARLY_INIT_F

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:32 -05:00
Simon Glass
a421192fb8 Convert CONFIG_ARCH_EARLY_INIT_R to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_EARLY_INIT_R

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 16:43:48 -05:00
Simon Glass
d02f5ea301 config: Drop CONFIG_ARCH_DMA_PIO_WORDS
This is not defined by any board in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 16:42:20 -05:00
Stefan Roese
27090324c2 arm64: mvebu: Armada 7040-db: Add SDHCI device tree nodes
This patch adds the SDHCI device tree nodes to the Armada 7040-db
dts file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
2017-01-25 07:04:12 +01:00
Stefan Roese
b14b0b1e7b arm64: mvebu: Armada 7k/8k: Add SDHCI device tree nodes
This patch adds the SDHCI device tree nodes to the Armada AP806 dtsi
file which is used by the Armada 7k/8K SoCs.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
2017-01-25 07:04:08 +01:00