Commit graph

12 commits

Author SHA1 Message Date
Bin Meng
02be57caf7 riscv: qemu: Enable usb keyboard as an input device
This brings PCI xHCI support to QEMU RISC-V and uses a usb keyboard
as one of the input devices.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:32:44 +08:00
Bin Meng
716161663e riscv: qemu: Enable Bochs video support
Enable video console using the emulated Bochs VGA card.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:31:52 +08:00
Heinrich Schuchardt
7556927fc0 doc: qemu-riscv: describe booting with QEMU and KVM
The ELF U-Boot image produced by qemu-riscv64_smode_defconfig can be
used to boot with QEMU and KVM.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-08-20 08:38:12 +02:00
Heinrich Schuchardt
16736c2312 doc: debug UART for RISC-V QEMU virt machine
Provide settings for enabling the debug UART of the virt machine on
RISC-V QEMU.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-04-09 21:06:31 +02:00
Anup Patel
7c08680aa3 doc: qemu-riscv: Update documentation for QEMU spike machine
We can now use same U-Boot images on both QEMU virt machine and QEMU
spike machine so let's update the QEMU RISC-V documentation.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-02-10 11:19:15 +08:00
Simon Glass
c3c1614537 arm: riscv: qemu: Explain how to extract the generated dt
QEMU currently generates a devicetree for use with U-Boot. Explain how to
obtain it.

Also explain how to merge it to produce a devicetree with the U-Boot
features included.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Atish Patra
24c5689447 doc: qemu-riscv: Fix opensbi build instructions
Latest opensbi uses generic platform for Qemu. Update the build
instructions.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:20 +08:00
Heinrich Schuchardt
f0b1831864 doc: qemu-riscv: describe attaching a disk image
How to add an emulated disk to QEMU may not be known to the user.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-17 15:09:22 +08:00
Bin Meng
ba51269f75 doc: qemu-riscv: Update QEMU run command
Explicitly pass the "-bios" option to QEMU to run U-Boot, instead
of the "-kernel" option, as we know that "-bios" behavior will be
changed since QEMU 5.1.0.

This also updates validated QEMU version to 5.0.0.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03 15:08:05 +08:00
Bin Meng
ed1475e2f4 riscv: qemu: Remove the simple-bus driver for the SoC node
Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a
"riscv-virtio-soc" compatible string, and a "simple-bus" driver
was created to accommodate that special case in U-Boot.

Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus",
hence the special simple-bus driver is no longer needed.

Update the doc to mention the latest tested QEMU version 4.2.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:06 +08:00
Lukas Auer
8313fcdb4f doc: update QEMU RISC-V documentation
The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Bin Meng
40046df739 doc: board: Convert README.qemu-riscv to reST
Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-24 10:07:24 -04:00
Renamed from doc/README.qemu-riscv (Browse further)