5 commits

Author	SHA1	Message	Date
Masahiro Yamada	620118403e	ARM: at91: collect SoC sources into mach-at91 ... This commit moves source files as follows: arch/arm/cpu/arm920t/at91/* -> arch/arm/mach-at91/arm920t/* arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/* arch/arm/cpu/armv7/at91/* -> arch/arm/mach-at91/armv7/* arch/arm/cpu/at91-common/* -> arch/arm/mach-at91/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>	2015-02-21 08:23:51 -05:00
Bo Shen	b54dd1b3ad	ARM: atmel: sama5d4: can access DDR in interleave mode ... The SAMAA5D4 SoC can access DDR in interleave mode. Signed-off-by: Bo Shen <voice.shen@atmel.com>	2015-02-07 23:42:51 +01:00
Heiko Schocher	7dd5891061	arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45 ... - compile mpddrc ram init code also for AT91SAM9M10G45 based boards. - in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>	2014-11-17 08:47:16 -05:00
Heiko Schocher	341f548ee9	arm, at91, mpddrc: fix typo in ddr2_init() ... use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>	2014-11-17 08:47:16 -05:00
Bo Shen	9d9289cb31	arm: atmel: add ddr2 initialization function ... The MPDDRC supports different type of SDRAM This patch add ddr2 initialization function Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>	2013-12-01 22:38:47 +01:00