To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
If the EEPROM could not be read or is corrupt we always want to hang.
Note that an error message will have been displayed by read_eeprom in this
case.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Certain features we desire require a larger stack than is available by using
iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that
we can use these features.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the SPL is to be used for Falcon mode then we need to make sure the SPL
disable the GSC boot watchdog.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
If the SPL is to be used for Falcon mode then we need to make sure it
configures basic GPIO (iomux, padconf, and default output levels).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Now that uart and i2c setup functions have been moved to common.c we can
use these and remove code duplication.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This fixes a regression caused by e25fbe3fe5
(gw_ventana: Move the DCD settings to spl code)
The clock gating must be setup prior to calling arch_cpu_init(). Without this
booting to SD (directly via eFuse or via bmode) will hang.
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit combines catching missing memory and calibration data into
one if() block. It further prints pertinent information in determining
why the failure occurred.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add memory configuration for an IMX6SDL + 1GB density DRAM.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Updated 16bit DDR calibration using values obtained from running the
i.MX6 DDR Stress Test tool over a set of boards over full operationg
temperature.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW551x is a small form factor board based on the IMX6 SoC that includes:
* up to 512MB DDR3 memory
* up to 2GB NAND flash
* 1x miniPCIe socket (with USB)
* HDMI out (micro-HDMI)
* HDMI in (micro-HDMI)
* TTL level I/O (supported by GW16111 breakout board):
* I2C
* 2x UART
* CAN
* 2x DIO (GPIO/PWM)
* USB OTG
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f (gw_ventana: Move the DCD settings to spl code)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Zeroing GD in board_init_f() is not needed any more. As its now done in
crt0.S. The patch that clears the GD in crt0.S is this one:
aae2aef9 [arm: Set up global data before board_init_f()] from Simon.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.
This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Switch to an SPL image. The SPL for Ventana does the following:
- setup i2c and read the factory programmed EEPROM to obtain DRAM config
and model for board-specific calibration data
- configure DRAM per CPU/size/layout/devices/calibration
- load u-boot.img from NAND and jump to it
This allows for a single SPL+u-boot.img to replace the previous multiple boa
configurations.
Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
