Commit graph

14 commits

Author SHA1 Message Date
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
ac727577f0 Revert "drivers/ddr/fsl: Dual-license DDR driver"
Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcaf.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-14 21:34:05 -05:00
York Sun
ee3556bcaf drivers/ddr/fsl: Dual-license DDR driver
To make this driver easier to be reused, dual-license DDR driver.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Tom Rini <trini@konsulko.com>
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Thomas Schaefer <thomas.schaefer@kontron.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Robert P. J. Day <rpjday@crashcourse.ca>
CC: Alexander Merkle <alexander.merkle@lauterbach.com>
CC: Joakim Tjernlund <joakim.tjernlund@transmode.se>
CC: Curt Brune <curt@cumulusnetworks.com>
CC: Valentin Longchamp <valentin.longchamp@keymile.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Ira W. Snyder <iws@ovro.caltech.edu>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Kyle Moffett <Kyle.D.Moffett@boeing.com>
CC: Sebastien Carlier <sebastien.carlier@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2018-02-09 08:36:40 -08:00
York Sun
140ad2d899 drivers/ddr/fsl: Cleanup unused variable
Variable "row_density" is no longer used. Drop it from DIMM structure.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30 09:14:07 -08:00
York Sun
564e9383e5 drivers/ddr/fsl: Add calculation of register control words
DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30 09:14:07 -08:00
York Sun
c0c32af0b2 drivers/ddr/fsl: Add 3DS RDIMM support
On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30 09:14:07 -08:00
York Sun
426230a65f drivers/ddr/fsl: Fix DDR4 RDIMM support
For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30 09:14:06 -08:00
York Sun
6b95be2280 driver/ddr/fsl: Fix driver to support empty first slot
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
York Sun
03e664d8f4 driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:18 -08:00
York Sun
789b3447c0 driver/ddr/fsl: Add workaround for faulty SPD
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
1d71efbb03 driver/ddr: Restruct driver to allow standalone memory space
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00