A few platforms recently added in CONFIG_DFU_MMC under include/configs
rather than via the defconfig, update them.
Signed-off-by: Tom Rini <trini@konsulko.com>
A couple of trivial fixes and improvements for ARC
Most notable are:
* Move of ENV_SIZE/ENV_OFFSET to Kconfig
* Fix with private structure allocation for arc_uart
* Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
Even though we don't use CONFIG_SYS_CACHELINE_SIZE in ARC-specific code
it is used a lot in different drivers for alignment purposes.
So we define it and make much more drivers at least compilable for ARC.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
"i" gets incremented before we're entering loop body
and effectively we iterate from 1 to 8 instead of 0 to 7.
This way we:
a) Skip the first line of struct hs_versions
b) Go over it and access memory beyond the structure
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Apparently we never allocated buffer for arc_serial_platdata
which for some reason never caused problems when executed in nSIM.
But in Qemu this causes expected problems.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Join the party of some ARM boards and drop more
items from include/configs/xxx.h.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_DW_SERIAL is no longer used anywhere so let's forget about it.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: "Jorg Krause" <joerg.krause@embedded.rocks>
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Print information about Aquantia system interface and firmware loaded
on the phy.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If System Interface protocol is USXGMII then enable USXGMII autoneg
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).
Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
ether_crc was added to the core net code in commit 53a5c424bf
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
Standard Registers)
Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.
Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]
Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.
The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.
Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.
Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10
interfaces (0..9) as the number can only have one digit.
On boards with more than 10 interfaces, this leads to the protection
and format checks being absent for eth10addr and above.
Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow
more than one digit.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
ETHADDR_WILDCARD is defined as the same value in both env_flags.h
and env_callback.h
As env_callback.h includes env_flags.h, remove the duplicate definition
from env_callback.h
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When dealing with two ethernet ports and having "netretry" set
to "once", it could occur that the connection (e.g. an ARP
request) failed, hence the status of the netloop was
"NETLOOP_FAIL". Due to the setting of "netretry", the network
logic would then switch to the other network interface,
assigning "ret" with the return value of "net_start_again()".
If this call succeeded we would return 0 (i.e. success) to
the caller when in reality the network action failed.
Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.
Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.
Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.
Fix the padding code to zero out the padded bytes at the end.
Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.
This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.
Fix this by correctly clearing the size mask before setting the new
length.
Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There is no i2c connected in base DT that's why disable I2C commands.
Also remove zynq_zybo which is not needed now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Most of the memory is being consumed by device binding code,
more space needed for other data structures.
Z-turn board has already hit the limit, others may follow soon.
Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):
root_driver: 108
mod_exp_sw: 108
amba: 120
serial@e0000000 aka uart0: 112
serial@e0001000 aka uart1: 88
spi@e000d000 aka qspi: 120
sdhci@e0100000 aka mmc0: 455
sdhci@e0100000.blk: 208
slcr@f8000000: 96
clkc@100: 72
(total) 1487 = 0x5cf of 0x600
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.
Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.
Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)
Zynq mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch enables CONFIG_REMAKE_ELF for Zynq platform
so that it generates u-boot.elf from binary which works
for all Zynq boards with OF_SEPARATE option enabled.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4)
ZynqMP mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bootrom is not capable to work with non aligned bootloader sizes.
SPL with OF_SEPARATE generates non-align images quite often that's
why this change is required before OF_SEPARATE enableding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable ISSI flash for platforms. Xilinx reference boards are also used
internally with different flash part to increase coverage that's why
enable also ISSI parts for all these boards even if that board is
released only with one part.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
