Rather than naming the phandle struct according to the number of cells it
uses (e.g. struct phandle_2_cell) name it according to the number of
arguments it has (e.g. struct phandle_1_arg). This is a more intuitive
naming.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Update this function to return more detail about a property that contains
phandles. This will allow (in a future commit) more accurate handling of
these properties.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
This function will need to have access to class members once we enhance it
to support multiple phandle values. In preparation for that, move it into
the class.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Now that the Fdt class can map phandles to the associated nodes, use that
instead of a separate implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add a map from phandles to nodes. This can be used by clients of the the
class instead of maintaining this themselves.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
At present dtoc assumes that all 'reg' properties have both an address and
a size. For I2C devices we do not have this. Adjust dtoc to cope.
Reported-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
When using 32-bit addresses dtoc works correctly. For 64-bit addresses it
does not since it ignores the #address-cells and #size-cells properties.
Update the tool to use fdt64_t as the element type for reg properties when
either the address or size is larger than one cell. Use the correct value
so that C code can obtain the information from the device tree easily.
Alos create a new type, fdt_val_t, which is defined to either fdt32_t or
fdt64_t depending on the word size of the machine. This type corresponds
to fdt_addr_t and fdt_size_t. Unfortunately we cannot just use those types
since they are defined to phys_addr_t and phys_size_t which use
'unsigned long' in the 32-bit case, rather than 'unsigned int'.
Add tests for the four combinations of address and size values (32/32,
64/64, 32/64, 64/32). Also update existing uses for rk3399 and rk3368
which now need to use the new fdt_val_t type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Large arrays can result in lines with hundreds or thousands of characters
which is not very editor-friendly. To avoid this, addjust the tool to
group values 8 per line.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
When dealing with multi-cell values we need a type that can hold this
value. Add this and a function to process it from a list of cell values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
We need to be able to search back up the tree for #address-cells and
#size-cells. Record the parent of each node to make this easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
In a0f3e3df4a we switched to using the Ubuntu-provided dtc as travis
was having a problem with the number of warnings that were generated by
the newer dtc. This is no longer a concern as we now have the same
logic as Linux to enable/disable additional more stringent warnings. Go
back to building dtc from source.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on travis-ci:
Tested-by: Simon Glass <sjg@chromium.org>
Checkpatch produces the following warning:
Unescaped left brace in regex is deprecated here
(and will be fatal in Perl 5.30), passed through in regex;
marked by <-- HERE in m/^(\+.*(?:do|\))){ <-- HERE /
at scripts/checkpatch.pl line 3348.
The curent checkpatch of the Linux kernel corrects this
bug and many others.
It provides improved colored output.
So replace checkpatch by the current Linux version.
Add an empty file scripts/const_structs.checkpatch.
We can later fill it according to our needs.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The strto functions should honor the specified base (if non-zero) rather
than permitting a hex or octal string when the user wanted (for example)
base 10.
This has been fixed somewhere along the way in the upstream linux kernel
src tree, at some point after these was copied in to u-boot. And also
in a way that duplicates less code. So port _parse_integer_fixup_radix()
to u-boot.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add unit tests for the 'gpt rename' and 'gpt swap' commands that
rely on the block device created by test/py/make_test_disk.py.
Add CONFIG_CMD_GPT_RENAME to the sandbox_defconfig. Remove the
testdisk.raw test device at the end of the tests.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Run unit tests for the 'gpt guid' command, making use of the block
device created by test/py/make_test_disk.py. Remove this device at
the end of the tests.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Provide a Python function that creates a small block device for the
purpose of testing the cmd/gpt.c or cmd/part.c functions in the u-boot
sandbox.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the kernel
definitions. Cleanup the old pinctrl macros from the common header
file so that they are not used by any new boards.
Signed-off-by: Suman Anna <s-anna@ti.com>
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the
kernel definitions. Fixup the current pinctrl data for the CompuLab
CL-SOM-AM57x board to use these new macros to facilitate the removal
of the old macros.
NOTE:
The PEN and PDIS macro values used previously were actually defined
inversely, a value of 1 in bit position 16 actually means that the
internal pullup/pulldown is disabled and not enabled as inferred by
PEN. So, previous pinmux config data such as (PDIS | PTU) is confusing
as it actually was meant for enabling internal pullup. The data is
fixed up only to be equivalent to the previous data.
Signed-off-by: Suman Anna <s-anna@ti.com>
To remove the assignment of CONFIG_SYS_EXTRA_OPTIONS option,
which is deprecated, use the CONFIG_XXXX_BOOT options to
indicate the boot media, and the SoC is selected by the board.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of
the CONFIG_SYS_USE_XXXX option, which is declared by
CONFIG_SYS_EXTRA_OPTIONS option.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
As said in READRE.kconfig, include/configs/*.h will be removed
after all options are switched to Kconfig. As the first step,
remove the follow line from include/configs/*.h.
#include <asm/hardware.h>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3
and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is
deprecated, add the SoC options to Kconfig.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2
with 1Gbit DDR2-SDRAM in a single package.
The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and
Mac-address EEPROM.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The SAMA5D2 SiP(System in Package) has different Chip IDs in the
CHIPID and CHIP_EXID registers.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the boot device for booting from the QSPI flash.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Because before switching to a lower clock source, we must switch
the clock source first instead of last. So before configuring the
PMC_MCKR register, invoke at91_mck_init_down() first.
As said in datasheet, the the size of SPL must not exceed the maximum
size allowed(64Kbytes).
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
rate while switching) from AT91Bootstrap.
While switching to a lower clock source, we must switch the clock
source first instead of last. Otherwise, we could end up with
too high frequency on internal bus and peripherals.
This happens on SAMA5D2 as exitting from the ROM code.
Add a function pmc_mck_init_down() to allow this sequence.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to
the crystal oscillator, a check must be carried out to ensure that
the oscillator is present and that its freqency is valid.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a function to display the company's logo and board information
via the API from DM_VIDEO. This function can be shared by other
atmel boards, so locate it in board/atmel/common folder.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to display the company's logo via the API of DM_VIDEO,
and add the logo files of both Atmel and Microchip.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For sama5d2, add the sfr node with syscon support.
In order to access the SFR_UTMICKTRIM register for the utmi clock
driver, add the phandle property for the utmi node to point to the
sfr node.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
By default, it is assumed that the UTMI clock is generated from
a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
clock in the proper way.
The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target
of 480 MHz.
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rate
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
[trini: Depend on SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
This section of the settings file may be missing. Handle that gracefully
rather than emitting an error.
Also update patman to write this section when a new settings file is
created.
Fixes: e11aa602 (patman: add support for omitting bouncing addresses)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.pckham@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The e-mail addresses for DA8XXEVM BOARD and DA850_AM18XXEVM BOARD
are invalid.
Remove DA8XXEVM.
Update DA850_AM18XXEVM to have me be the maintainer since I work
for Logic PD and have access to OMAP-L138 and AM1808 EVM kits.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_EMIF4
CONFIG_SDRC
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefano Babic <sbabic@denx.de>
There was a check for CONFIG_MAC_ADDR_IN_EEPROM and
a check for CONFIG_MAC_ADDR_IN_SPIFLASH, however
some of the EEPROM related code wasn't encapsulated
inside the #if defined statement so the EEPROM code
could get executed even when it wasn't explicitly
enabled or wanted.
Signed-off-by: Adam Ford <aford173@gmail.com>
In mancy cases both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR point
to an otherwise-unused SMNAND_ENV_OFFSET.
This patch will set both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR to
whatever value was defined by SMNAND_ENV_OFFSET.
Signed-off-by: Adam Ford <aford173@gmail.com>
The DTS files had some spacing issues and they needed fixing. This
pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5.
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.
Signed-off-by: Adam Ford <aford173@gmail.com>
V3: The resync broke card detect on MMC1 on Logic PD's Torpedo,
so we add the cd-invert to the Torpedo's -u-boot.dtsi file.
V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo
Remove the need for the second patch in the series
Either the USB and Fastboot were never finished, or somehow it got
lost. This puts enough hooks back into omap3logic to enable
fastboot and hopefully prepare it for Kconfig conversion.
Signed-off-by: Adam Ford <aford173@gmail.com>
Fix the building warning as below:
---8<----
Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50
Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50
--->8----
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some device the serial console's initialization cannot run early during
the boot process. Hence, nulldev serial device is helpful on that
situation.
For example, if the serial module was implemented in FPGA. Serial
initialization is prohibited to run until the FPGA was programmed.
This commit is to adding nulldev serial driver. This will allows the
default console to be specified as a nulldev.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
With debug enabled, SPL output following these debug prints is on the
same line and it is hard to read. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit adds support for GPIO reset lines matching the
common linux "reset-gpios" devicetree binding.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Add support for detection
of SR2.1 version of DRA71x family of processors.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
