Commit graph

3 commits

Author SHA1 Message Date
Pragnesh Patel
bbb94af981 riscv: Add _image_binary_end for SPL
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Rick Chen
444c46413f riscv: Fix clear bss loop in the start-up code
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Lukas Auer
8c59f2023c riscv: add SPL support
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00