Commit graph

4 commits

Author SHA1 Message Date
Kumar Gala
5df4b0ad0d powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq().  If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Dave Liu
b4983e16d1 fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Jon Loeliger
39aa1a7348 FSL DDR: Convert MPC8610HPCD to new DDR code.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 02:06:03 +02:00