Commit graph

172 commits

Author SHA1 Message Date
Masahiro Yamada
55ce920d5f ARM: socfpga: abolish CONFIG_SOCFPGA
Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:21:17 +02:00
Masahiro Yamada
05a217212b ARM: socfpga: move SoC sources to mach-socfpga
Our recent trend is to collect SoC files into arch/arm/mach-(SOC).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:21:12 +02:00
Dinh Nguyen
18ad2de4b2 arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc
We need to adjust the SYS_INIT_RAM_SIZE to have room for the
SPL_MALLOC_SIZE.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
a717b811ff arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
6868160ab1 arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:16 +02:00
Simon Glass
ef48f6dd30 Kconfig: Move CONFIG_DESIGNWARE_ETH to Kconfig
Move this to Kconfig and clean up board config files that use it. Also
rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists
in drivers/net/Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
Version 1:
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-18 11:11:36 -06:00
Marek Vasut
d7a73038f5 arm: socfpga: Zap board_early_init_f()
Zap this unused empty function, no point in having it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
7287d5f091 arm: socfpga: Zap checkboard()
Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT "model"
property.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Simon Glass
0f36f957f4 dm: socfpga: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:35 -07:00
Stefan Roese
d0e932de7c arm: socfpga: Change watchdog timeout
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.

Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-12-21 14:39:04 +01:00
Stefan Roese
0edeba054b arm: socfpga: DW_SPI: Remove clock info from config header
Remove the now unnecessary clocking info from the SoCFPGA
config header. As this info in now used directly in the SPI driver
itself.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
a6e7359181 arm: socfpga: Add Designware (DW) SPI support to config header
Enable support for the DW master SPI controller in the config header
for the SoCFPGA. This controller can only be enabled, if DT support
is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
7fb0f59649 arm: socfpga: Add Cadence QSPI support to config header
With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Masahiro Yamada
3fcfe80377 ARM: remove CONFIG_ARMV7 defines
Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-11-20 11:28:24 -05:00
Tom Rini
c88eaea0a0 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-11-11 16:59:44 -05:00
Marek Vasut
0223a95c72 arm: socfpga: Add example UDC config
Add example of an USB UDC configuration with DFU and UMS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-07 16:32:02 +01:00
Marek Vasut
8a78ca9ea5 arm: socfpga: Add example config entry for EPCS/EPCQ SPI
Add example config file entry for the Altera SPI controller. This SPI
controller can also, under special conditions, be used to operate the
EPCS/EPCQ SPI NOR.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-31 10:18:05 +01:00
Stefan Roese
ebcaf966ed arm: socfpga: Add I2C support to SoCFPGA
This patch adds I2C support for the SoCFPGA. Using the designware I2C
controller driver. It supports all 4 I2C busses on the SoCFPGA.

The designware I2C driver has now been converted to the
CONFIG_SYS_I2C framework. So lets enable it on SoCFPGA.

Tested on SoCrates.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2014-10-30 10:17:47 +01:00
Marek Vasut
20cadbbe2e arm: socfpga: config: Add USB support example
Add example configuration stub for the DWC2 USB controller.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>
2014-10-27 02:26:24 +01:00
Marek Vasut
34584d190d arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-27 02:26:24 +01:00
Marek Vasut
fc520894d4 arm: socfpga: Move code from misc_init_r() to arch_early_init_r()
Move this initialization code to proper place. The misc_init_r()
function is called way too late and the platform initialization
code should be executed much earlier.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-27 02:26:24 +01:00
Pavel Machek
5095ee088d arm: socfpga: Split SoCFPGA configuration
Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.

This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:51 +02:00