Commit graph

7 commits

Author SHA1 Message Date
Leo Yu-Chi Liang
936b503030 andes: ae350: Save cpu name to env
Detect CPU name through marchid and then save it to env.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:11 +08:00
Leo Yu-Chi Liang
b0469041c0 andes: ae350: Implement cache switch via Kconfig
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Tom Rini
0b9441ae76 riscv: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-24 16:34:45 -04:00
Tom Rini
eea6227d1f ae350: Update defconfig list
Update the list of defconfigs, this was missed with the last pull
request of the u-boot-riscv tree.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 11:40:44 -04:00
Randolph
03a4504659 riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.

Moving the DTB in front of the kernel can avoid this error.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19 17:29:33 +08:00
Randolph
b68bf22fbb configs: andes: add vender prefix for target name
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350"

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-10-04 18:00:51 +08:00
Leo Yu-Chi Liang
8900e2bbec riscv: Rename Andes cpu and board names
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00