Commit graph

31083 commits

Author SHA1 Message Date
Guillaume GARDET
4c5bbc2328 spl: if MMCSD_MODE_RAW fails, try MMCSD_MODE_FS, if available
In SPL MMC, boot modes are exclusive. So, if MMCSD_MODE_RAW fails, the board hangs. This patch allows to
try MMCSD_MODE_FS then, if available.

It has been tested on a pandaboard (rev. A3).

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
2014-12-08 09:35:42 -05:00
Heiko Schocher
69337a9d79 MAINTAINERS: add me as a maintainer of UBI
Add me for UBI custodian.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
2014-12-08 09:35:41 -05:00
Wu, Josh
ecec4e9c82 net: bootp: as CONFIG_BOOTP_SERVERIP is defined, keep bootfile not changed
Currenly when CONFIG_BOOTP_SERVERIP is defined, the SERVERIP is not changed
when receive the BOOTP packet. But BOOTFILE is changed via BOOTP packet.

As we will load the BOOTFILE from SERVERIP, if the BOOTFILE is modified
by bootp packet but SERVERIP is not, that is not make sense.

This patch make SERVERIP and BOOTFILE be consistent. If we define the
CONFIG_BOOTP_SERVERIP, then SERVERIP and BOOTFILE will not changed by
BOOTP packet. Only IP address is changed.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2014-12-08 09:35:41 -05:00
Daniel Schwierzeck
27e77183a1 get_maintainer.pl: fix source tree detection
get_maintainer.pl always fails with following message:
./scripts/get_maintainer.pl: The current directory does not appear to be a linux kernel source tree.

This was caused by commit:

commit 548b310c68
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
Date:   Thu Oct 30 15:50:15 2014 +0900

    Remove the CREDITS file

    This file is not maintained these days.

    We use MAINTAINERS for the maintainership of the supported boards.
    For dead boards, we have some clues in doc/README.scrapyard and
    also imperishable history in git-log.

Remove CREDITS from source tree detection to fix this.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:41 -05:00
Simon Glass
d8727713b6 Fix console functions for U-Boot API
Commit 709ea54 made a subtle change to the way the U-Boot API jump table
is set up. So at present putc(), getc(), tstc() and puts() do not work
correctly from functions that use the U-Boot API.

Previously these were set to the stdio functions, but these now take a
parameter specifying which stdio device to use. Instead, we should change
them to use the global functions which do not have a parameter.

This is a slight change in behaviour. The functions will now output to
all selected stdio devices - for example putc() will output a character to
all devices selected by stdout. However in most cases there is only one,
and it isn't necessarily incorrect behaviour anyway.

The API version is not changed since it is compatible with what was there
before.

Reported-by: Martin Dorwig <dorwig@tektronik.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:41 -05:00
Paul Kocialkowski
b97300b62f spl: MMC U-Boot image load from raw partition
Raw images of U-Boot can be stored inside MMC partitions, so it makes sense to
read the partition table, looking for a partition number instead of using
a fixed sector address.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Only add mmc_load_image_raw_partition() when
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to avoid warning, add missing
conversion in spl_mmc_load_image()]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-08 09:35:06 -05:00
Mark Tomlinson
f4ed36964a i2c: Correct spelling error
"diconnect" and "disconnet" should both be "disconnect".

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:22 +01:00
Mark Tomlinson
2fe50ef403 i2c: Fix deselection of muxes
Due to an uninitialised variable, when muxes were deselected, any value
could be written to the mux control register. On the PCA9548, this could
result in multiple channels being selected, thus enabling multiple
pull-up resistors, and much bus capacitance.

The fix is simply to initialise the written value to zero.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:06 +01:00
Masahiro Yamada
f5d0b9b2c3 ARM: UniPhier: merge UniPhier config headers into a single file
Some configurations have been moved to Kconfig and the difference
among the config headers of UniPhier SoC variants is getting smaller
and smaller.  Now is a good time to merge them into a single file.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
3201455d6a ARM: UniPhier: move support card select to Kconfig
There are two kinds of expansion boards which are often used for
the UniPhier platform and they are only exclusively selectable.
It can be better described by the "choice" menu of Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
84b3584f21 ARM: UniPhier: move CONFIG_UNIPHIER_SMP to Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
b115678bdf ARM: UniPhier: use boot_is_swapped() macro for readability
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
8dca1d6f80 ARM: UniPhier: disable autostart by default
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
70879a9256 flash: do not fail even if flash_size is zero
CONFIG_SYS_MAX_FLASH_BANKS_DETECT allows to determine the number of
flash banks at run-time, that is, there is a possibility that no flash
bank is found.  Even in such cases, it makes sense to continue the
boot process without any flash device.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
2014-12-08 01:25:28 +09:00
Masahiro Yamada
9248a78f40 ARM: UniPhier: remove Denali NAND controller fixup code
This ugly work-around code is unnecessary since commit f09eb52b3f
(mtd: denali: set some registers after nand_scan_ident()).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-07 17:47:32 +09:00
Dinh Nguyen
b9b5cf0ea3 socfpga: correctly increment freeze_controller_base address
Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:53:57 +01:00
Dinh Nguyen
5d2f930de0 socfpga: add missing struct member fifo_triple_byte
socfpga_scan_manager structure was missing a data member.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:53:57 +01:00
Stefan Roese
0edeba054b arm: socfpga: DW_SPI: Remove clock info from config header
Remove the now unnecessary clocking info from the SoCFPGA
config header. As this info in now used directly in the SPI driver
itself.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
a72f80208d spi: designware_spi: Some fixes / changes
As suggested by Pavel, here some fixes to the designware SPI driver:

- Spelling fixes
- Comment for timeout added
- Removed n_bytes completely (bits_per_word is enough for this)
- Unput clock now not defined via macro. The function to
  get the clock value is now called directly from within the driver

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
481549f8c1 arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
c877eaa8a0 arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bits
As suggested by Pavel, lets combine the two calls into one.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
f37a126692 arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiers
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
a6e7359181 arm: socfpga: Add Designware (DW) SPI support to config header
Enable support for the DW master SPI controller in the config header
for the SoCFPGA. This controller can only be enabled, if DT support
is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
369164042e arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
ae79e2d298 arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
5bef6fd79f spi: Add designware master SPI DM driver used on SoCFPGA
This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.

This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
7fb0f59649 arm: socfpga: Add Cadence QSPI support to config header
With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
60896653d5 arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
881f6a448f arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
10e8bf88c0 spi: Add Cadence QSPI DM driver used by SoCFPGA
This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
5bf1f1ed13 arm: socfpga: dts: Move to SPDX license identifiers
The socfpga dts files are copied from the Rocketboards.org repository.
In U-Boot we usually replace the full-blown license header text with
the SPDX license identifiers. Lets do this for these new dts files
as well.

I just forgot to do this while adding the DT support for socfpga.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
2014-12-06 13:51:54 +01:00
Dinh Nguyen
74ae12e184 arm: socfpga: set skew settings for ethernet phy
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:51:54 +01:00
Stefan Roese
fa8278d702 arm: socfpga: Add myself as maintainer for the SoCrates board
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-06 13:51:54 +01:00
Minghuan Lian
af7219de2c powerpc/hydra: fix judging condition of RGMII selection
BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:17 -08:00
Chunhe Lan
b41f126340 powerpc/hydra: Update MDIO mux fixups
The new device trees use a more generic interface for
supporting muxing mdio buses. The mux property is thus
specified in "reg", rather than "fsl,hydra-mdio-muxval".

In order to support using old device trees, we keep the
old fixup in there. Linux will therefore see the both
properties, but will ignore fsl,hydra-mdio-muxval.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Xiaobo Xie
929dfdc26a powerpc/t4240rdb: enable eSDHC 3.3V support
The SD supply Voltage was 3.3V on T4240RDB, so enabled 3.3V support for eSDHC.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Wujie Qiu <B49553@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Tudor Laurentiu
8d3eaa9709 powerpc/mpc85xx: use correct dma compatible for several SoCs
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
 T1023/4, T1040, T2080/1, T4240, B4860.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
10227aaa24 board/t1024qds: add retimer support on t1024qds
Initialize retimer for XFI on t1024qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
5818643bf4 t1024qds: increase IO drive strength
Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
355b385847 board/t1024qds: update pin multiplexing
Add multiplexing support among SPI flash, TDM riser card and SDXC.
it routes SPI pins to SPI flash by default.
Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig.
Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm"
is set in hwconfig.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
cc19c25e27 net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
48c6f328f0 powerpc/t1024rdb: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.

T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two  Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
aba8004818 powerpc/t1024qds: Add T1024 QDS board support
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
789b3447c0 driver/ddr/fsl: Add workaround for faulty SPD
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Priyanka Jain
2892ec5f43 powerpc/mpc85xx: Update LIODN entries for T1040
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shengzhou Liu
06b3acf184 powerpc/t2080: updating rcw for silicon v1.1
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Suresh Gupta
e2544e7a54 B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
b24f6d401c powerpc/b4860qds: add workaround for XFI
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.

A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00