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8 commits

Author SHA1 Message Date
Michal Simek
c5cd2d2aba arm: dts: xilinx: Remove undocumented is-dual property 
Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15980560b98672959a889ff9970cbe9540b4ed69.1695808563.git.michal.simek@amd.com
 2023-10-09 12:13:04 +02:00
Simon Glass
8c103c33fb dm: dts: Convert driver model tags to use new schema 
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-02-14 09:43:26 -07:00
Raju Kumar Pothuraju
bc353102a0 xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP) 
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:

Zynq> sf probe 0 0 0
 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00  Failed to initialize SPI flash at 0:0 (error -2)

Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2021-08-26 08:08:11 +02:00
Luis Araneda
9896dc6558 ARM: dts: zynq: correct and improve the model property of dt files 
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2019-02-15 15:04:00 +01:00
Michal Simek
051a8ad7bb arm: zynq: Sync up licenses with mainline kernel 
Use different location for SPDX line. Also update dates for new mainline
DTS files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-04-09 12:14:49 +02:00
Michal Simek
03bc69dec9 arm: zynq: Remove 0x prefixes from cc108 
The patch fixing issues reported by DTC:
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have
leading "0x"

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-04-09 12:14:49 +02:00
Michal Simek
d78b4ae06a arm: zynq: Mark cc108 uart to be initialized before relocation 
The same change is done for others zynq boards to get uart as early as
possible.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-01-30 14:29:37 +01:00
Michal Simek
bc133e80ae arm: zynq: Add board support for cc108 
cc108 board is wiring uart via PL which is good platform for SPL fpga
support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2017-11-28 16:08:40 +01:00