Commit graph

20 commits

Author SHA1 Message Date
Simon Goldschmidt
42a37d9774 arm: socfpga: gen5: sync devicetrees to Linux
This is again a sync to linux-next + pending patches in Dinh's tree at
commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset
properties")'

It adds missing peripheral reset properties to socfpga.dtsi and removes
U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:15 +02:00
Simon Goldschmidt
e8dd60d489 arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
This fixes the board's dts to supply SPL with QSPI info.

The EBV Socrates board has DIP switches to boot from SD card or
QSPI, so let's fix its defconfig to work for both cases.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
c402e81702 dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)

Adapt board dts files that are not in Linux to keep their old
behaviour.

Change licenses to SPDX.

(Patman warnings/errors are in 1:1 copied files from Linux)

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
79a436d568 arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Simon Goldschmidt
a6fbf94550 arm: socfpga: fix qspi flash compatible (add "spi-flash")
This patch adds "spi-flash" to the compatible list of the qspi flash
chip for all socfpga boards. This is required to make qspi work on
these boards on top of the recent fixes. Without the "spi-flash"
compatible string for the flash chip, the speed cannot be read and a
speed of 0Hz is used (which results in a divide-by-zero on these
boards).

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-02-15 13:45:15 +01:00
Jason Rush
6e62b178e1 dts: cadence_spi: Sync DT bindings with Linux
Adopt the Linux DT bindings and clean-up duplicate
and unused values.

Fix indentation of the QSPI node in the keystone k2g
device tree.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-01-24 12:07:50 +05:30
Marek Vasut
268da813c7 ARM: socfpga: Disable USB OC protection on SoCrates
This is mandatory, otherwise the USB does not work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2016-05-06 18:41:49 +02:00
Stefan Roese
43809cfa1b arm: socfpga: socrates: Add eth0 alias to enable ethernet
This enables full ethernet usage, including U-Boot to write the board
specific MAC address (ethaddr) into the DT blob before passing it to
Linux.

Without this, the ethaddr is not detected in U-Boot at all, resulting
in this error upon bootup:

...
Model: EBV SOCrates
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
b5a5d2bd96 arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:51 +01:00
Marek Vasut
5d8546efa7 arm: socfpga: socrates: Add missing PHY skew config
Add missing KSZ9021 PHY skew configuration for the EBV socrates board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:49 +01:00
Marek Vasut
856b30dae5 arm: socfpga: Repair SoCrates board
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-30 13:30:19 +01:00
Marek Vasut
c2624240dd arm: socfpga: Do not enable gmac1 in Cyclone V dtsi
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
afe139938a arm: socfpga: Make the DT mmc node consistent
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
b09b72d83b arm: dts: socfpga: Fix SPI aliases
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.

So fix it such that we move these into socfpga.dtsi and make them use
the usual handles.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:04 +02:00
Stefan Roese
369164042e arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
60896653d5 arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
881f6a448f arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
5bf1f1ed13 arm: socfpga: dts: Move to SPDX license identifiers
The socfpga dts files are copied from the Rocketboards.org repository.
In U-Boot we usually replace the full-blown license header text with
the SPDX license identifiers. Lets do this for these new dts files
as well.

I just forgot to do this while adding the DT support for socfpga.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
2014-12-06 13:51:54 +01:00
Stefan Roese
51c580c6c9 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target
This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2014-11-07 15:58:31 +01:00