Commit graph

4 commits

Author SHA1 Message Date
Przemyslaw Marczak
3349682c77 dts:exynos:update pinctrl size-cells and fix child regs
This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.

Tested on:
- Odroid U3
- Odroid XU3

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2016-03-17 21:27:39 -06:00
Simon Glass
5b5e9ba3f7 exynos: sandbox: ti: Add SPDX license identifiers and notes
For some files I neglected to add a license. Rectify this:

arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
arch/arm/dts/s5pc100-pinctrl.dtsi
arch/arm/dts/s5pc110-pinctrl.dtsi

This file came from Linux and has no license information there, so add a
comment to that effect:

arch/sandbox/include/asm/bitops.h

This file also came from Linux - presumably someone from TI could add the
license:

include/dt-bindings/pinctrl/omap.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
2015-04-22 11:16:26 -06:00
Przemyslaw Marczak
523943d429 exynos4210: dts: fix gpio offset in pinctrl-uboot
The gpy0 don't need any additional register offset,
but the gpx0 does, so now it is fixed.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 19:21:07 -06:00
Simon Glass
c6b0b09032 dm: exynos: dts: Adjust device tree files for U-Boot
The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:35:57 -06:00