This MTD part infrastructure will be used by the upcoming
UBI support.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a problem on systems where the NOR flash is attached
to a 64 bit bus. The toggle bit detection in flash_toggle() is based
on the assumption that the same flash address is read twice without
any other interjacent flash accesses. However, on 32 bit systems the
function flash_read64() [as currently implemented] does not perform
an atomic 64 bit read - instead, this is broken down into two 32 bit
read accesses on addresses "addr" and "addr + 4". So instead of
reading a 64 bit value twice from "addr", we see a sequence of 4 32
bit reads from "addr", "addr + 4", "addr", and "addr + 4". The
consequence is that flash_toggle() fails to work.
This patch implements a simple, but somewhat ugly solution, as it
avoids the use of flash_read64() in this critical place (by breaking
it down manually into 32 bit read operations) instead of rewriting
flash_read64() such to perform atomic 64 bit reads as one could
expect. However, such a rewrite would require the use of floating
point load operations, which becomes pretty complex:
save MSR;
set Floating Point Enable bit in MSR;
use "lfd" instruction to perform atomic 64 bit read;
use "stfd" to store value to temporary variable on stack;
load u64 value from temporary variable;
restore saved MSR;
return u64 value;
The benefit-cost ratio of such an implementation was considered too
bad to actually attempt this, especially as we can expect that such
an implementation would not only have a bigger memory footprint but
also cause a performance degradation.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
As reported by Ilko Iliev <iliev@ronetix.at>, the "nand erase clean"
command is currently broken, and among other things causes all blocks
to be marked bad.
This implements it properly using MTD_OOB_AUTO, along with some
indentation fixes.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Hardware expects ECCM 0 for small page and ECCM 1 for large page
when booting from NAND, so use those defaults.
Signed-off-by: Scott Wood <scottwood@freescale.com>
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Some chips require a RESET after power-up (e.g. Micron MT29FxGxxxxx).
The first command sent is NAND_CMD_READID.
Issue a NAND_CMD_RESET in nand_scan_ident before reading the device id.
Tested with an MT29F4G08AAC.
Signed-off-by: Karl Beldan <karl.beldan@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This brings the core NAND code up to date with the Linux kernel.
Since there were several drivers in Linux as of the last update that are
not in u-boot, I'm not bringing over new drivers that have been added
since in the absence of an interested party.
I did not update OneNAND since it was recently synced by Kyungmin Park,
and I'm not sure exactly what the common ancestor is.
Signed-off-by: Scott Wood <scottwood@freescale.com>
When the total size of all NAND devices exceeds 4 GiB, the size will
overflow. This patch tries to fix this.
Note that we still have a problem when a single NAND device is bigger
than 4 GiB: then the overflow would actually happen earlier, i. e.
when storing the size in nand_info[].size, as nand_info[].size is an
"u_int32_t".
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
The flash_unlock_seq requires a sector for AMD_LEGACY.
Fix a retcode check typeo.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The CFI flash driver starts at flash_init() which calls down into
flash_get_size(). This starts by calling flash_detect_cfi(). If said
function fails, flash_get_size() finishes by attempting to reset the
flash. Unfortunately, it does this with an info->portwidth set to 0x10
which filters down into flash_make_cmd() and that happily smashes the
stack by sticking info->portwidth bytes into a cfiword_t variable that
lives on the stack. On a 64bit system you probably won't notice, but
killing the last 8 bytes on a 32bit system usually leads to a corrupt
return address. Which is what happens on a Blackfin system.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch deletes oobavail assignments, they're calculated by the nand
core code in nand_scan_tail, plus current oobavail values are wrong for
the LP NANDs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch implements support for flash-based BBT for chips working
through ELBC NAND controller, so that NAND core will not have to re-scan
for bad blocks on every boot.
Because ELBC controller may provide HW-generated ECCs we should adjust
bbt pattern and bbt version positions in the OOB free area.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For large page chips, nand_bbt is looking into OOB area, and checking
for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
reserved for bbt means.
But ELBC driver is specifying ecclayout so that oobfree area starts at
offset 1, so only one byte left for the bbt purposes.
This causes problems with any OOB users, namely JFFS2: after first mount
JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
And on the next boot, NAND core will rescan for bad blocks, then will
see "0xff 0x19" pattern, and will mark all blocks as bad ones.
To fix the issue we should implement our own bad block pattern: just one
byte at OOB start. Though, this will work only for x8 chips. For x16
chips two bytes must be checked. Since ELBC driver does not support x16
NANDs (yet), we're safe for now.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fix printf format-string/arg mismatches under -DDEBUG.
These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx. Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch fixes a missing vendor code in the flash_real_protect() function.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
New implement sector lock and unlock or softlock commands
do not exist in AMD legacy flash. Thus, causing issue
when erasing AMD legacy flash (such as lv040)
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since page size field is changed from oobblock to writesize. But OneNAND is not updated.
- fix bufferram management at erase operation
This patch includes the NAND/OneNAND state filed too.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
onenand_print_device_info():
- Now returns a string to be placed in mtd->name,
rather than calling printf.
- Remove verbose parameter as it becomes useless.
Signed-off-by: Fathi Boudra <fabo@debian.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fixes an issue with chip->state not always being set causing troubles.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Rather than scanning on boot, scan upon the first attempt to check the
badness of a block. This speeds up boot when not using NAND, and reduces
the likelihood of needing to reflash via JTAG if NAND becomes
nonfunctional.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Implement block-skipping read/write, based on a patch from
Morten Ebbell Hestens <morten.hestnes@tandberg.com>.
Signed-off-by: Morten Ebbell Hestnes <morten.hestnes@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The hardware has separate registers for block and page-within-block,
but the division between the two has no apparent relation to the
actual erase block size of the NAND chip.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Using current driver elbc sometimes hangs during nand write. Reading back
last byte helps though (thanks to Scott Wood for the idea).
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This is a driver for the Flash Control Machine of the enhanched Local Bus
Controller found on some Freescale chips (such as the mpc8313 and the
mpc8379).
Signed-off-by: Scott Wood <scottwood@freescale.com>
Some hardware, such as the enhanced local bus controller used on some
mpc83xx chips, does ecc transparently when reading and writing data, rather
than providing a generic calculate/correct mechanism that can be exported to
the nand subsystem.
The subsystem should not BUG() when calculate, correct, or hwctl are
missing, if the methods that call them have been overridden.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch turns off printing of bad blocks per default upon bootup.
This can always be shown via the "nand bad" command later.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch changes nand_wait_ready() to not just call nand_wait(),
since this will send a new command to the NAND chip. We just want to
wait for the chip to become ready here.
Signed-off-by: Stefan Roese <sr@denx.de>
- Fixing leading white spaces
- Fixing indentation where 4 spaces are used instead of tab
- Removing C++ comments (//), wherever I introduced them
Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.
This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.
MAKEALL ppc/arm has some issues:
* DOC/OneNand/nand_spl is not building (I have not tried porting
these parts, and since I do not have any HW and I am not familiar
with this code/HW I think its best left to someone else.)
Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
cpu/ppc4xx/ndfc.c
cpu/arm926ejs/davinci/nand.c
board/delta/nand.c
board/zylonite/nand.c
Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Stig Olsen <stig.olsen@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The block and page parameters of onenand_verify_page() are not used. This causes a compiler error when CONFIG_MTD_ONENAND_VERIFY_WRITE is enabled.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
The CFI driver allowed only for static initializers in the
CFG_FLASH_BANKS_LIST definition, i. e. it did not allow to map
several flash banks contiguously if the bank sizes were not known in
advance, which kind of violates U-Boot's design philosophy.
(will be used for example by the TQM8xxL boards)
Signed-off-by: Wolfgang Denk <wd@denx.de>
Some of the flash memories produced by ATMEL start in read-only mode.
We need to unprotect it. This patch allows the AT49BV6416 to work with
cfi_flash memories. Tested in the at91rm9200ek board.
Signed-off-by: Rafael Campos Las Heras <rafael.campos@hanscan.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This got broken by commits 93c56f212c
[cfi_flash: support of long cmd in U-boot.]
That command needs to be in little endian format on BE machines
with CFG_WRITE_SWAPPED_DATA. Without this patch, the command 0xf0
gets saved on stack as 0x00 00 00 f0 and 0x00 gets written into
the cmdbuf in case portwidth = chipwidth = 8bit.
Cc: Alexey Korolev <akorolev@infradead.org>
Cc: Vasiliy Leonenko <vasiliy.leonenko@mail.ru>
Signed-off-by: Sebastian Siewior <bigeasy@linutronix.de>
This got changed by commit 93c56f212c
[cfi_flash: support of long cmd in U-boot.]
Long is the wrong type because it will behave differently on 64bit
machines in a way that is probably not expected. u32 should be
enough.
Cc: Alexey Korolev <akorolev@infradead.org>
Cc: Vasiliy Leonenko <vasiliy.leonenko@mail.ru>
Signed-off-by: Sebastian Siewior <bigeasy@linutronix.de>
Some boards based on AT91SAM926X-EK use smaller DF chips to keep
bootstrap, u-boot and its environment, using NAND or other external
storage for kernel and rootfs. This patch adds support for
small 1024x263 chip.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
This patch fixes NAND related printf format warning. Those warnings are
now visible since patch dc4b0b38d4
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.
Signed-off-by: Stefan Roese <sr@denx.de>
This is particularly problematic now that non-NAND-specific code is
including <nand.h>, and thus all debugging code is being compiled
regardless of whether it was requested, as reported by Scott McNutt
<smcnutt@psyent.com>.
Signed-off-by: Scott Wood <scottwood@freescale.com>
As pointed out by Jerry Hicks, this patch corrects the device ID of
the Spansion AM29DL800BB NOR device. Verified against latest Spansion
datasheet (rev C4 from Dezember 2006).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch simplifies flash_toggle() (AMD commandset), which is used to
detect if a FLASH device is still busy with erase/program operations. On
800MHz Canyonlands/Glacier boards (460EX/GT) the current implementation
did not detect the busy state reliably, resulting in non erased sectors
etc. This patch now simplifies this function by "just" comparing the
complete data-word instead of ANDing it with the command-word (0x40)
before the compatison. It is done the same way in the Linux implementation
chip_ready() in cfi_cmdset_0002.c.
Signed-off-by: Stefan Roese <sr@denx.de>
This is a re-write of the NAND FSL UPM driver using the more universal
hwcontrol callback (instead of the cmdfunc callback). Here is a brief
list of furher modifications:
- For the time being, the UPM setup writing the UPM array has been
removed from the driver and must now be done by the board specific
code.
- The bus width definition in "struct fsl_upm_nand" is now in bits to
comply with the corresponding Linux driver and 8, 16 and 32 bit
accesses are supported.
- chip->dev_read is only set if fun->dev_ready != NULL, which is
required for boards not connecting the R/B pin.
- A few issue have been fixed with MxMR bit manipulation like in the
corresponding Linux driver.
Note: I think the "io_addr" field of "struct fsl_upm" could be removed
as well, because the address is already determined by
"nand->IO_ADDR_[RW]", but I'm not 100% sure.
This patch has been tested on a TQM8548 modules with the NAND chip
Micron MT29F8G08FABWP.
This patch is based on the following patches posted to this list a few
minutes ago:
PPC: add accessor macros to clear and set bits in one shot
83xx/85xx/86xx: add more MxMR local bus definitions
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Added new command set ID. Buffered write command processing is changed
in order to support M18 flash chips family.
Signed-off-by: Alexey Korolev <akorolev@infradead.org>
Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko@mail.ru>
Some NOR flash chips needs support of commands with length grether than max
value size of uchar. For example all M18 family chips use 0x1ff command in
buffered write mode as value of program loops count.
Signed-off-by: Alexey Korolev <akorolev@infradead.org>
Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko@mail.ru>
This adds a new SPI flash subsystem.
Currently, only AT45 DataFlash in non-power-of-two mode is supported,
but some preliminary support for other flash types is in place as
well.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* The cfi_flash.c memset fix actual allows the board to boot so there is
a bit more going on here than just resolving warnings associated with
uninitialized variables.
* include/asm/bitops.h:302: warning: '__swab32p' is static but used in
inline function 'ext2_find_next_zero_bit' which is not static
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Onenand needs a version of memcpy() which performs 16 bit accesses
only; make sure the name does not conflict with the standard
function.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch adds a configurable flash auto protection list that can be used
to make U-Boot protect flash regions in flash_init().
The idea has been discussed on the u-boot mailing list starting
on Nov 18th, 2007.
Even this patch brings a new feature it is used as a bugfix for 4xx
platforms where flash_init() does not completely protect the
monitor's flash range in all situations.
U-Boot protects the flash range from CFG_MONITOR_BASE to
(CFG_MONITOR_BASE + monitor_flash_len - 1) by default. This does not
include the reset vector at 0xfffffffc.
Example:
#define CFG_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
This config option will auto protect the last 512k of flash that
contains the bootloader on board like APC405 and PMC405.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch correctly sets the oobavail variable
and fixes a bug where the oob data was not valid when
there where multiple groups in oobfree.
First segment fixes a typo
Second segment fixes a bug where oob data may be copied incorrectly.
Third segment adds an error message when exiting due to write protect.
Forth segment fixes a bug where oobavail may be set incorrectly.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
This patch removes the board dependent parts from
"drivers/mtd/dataflash.c".
Each board relying on this, will have the appropriate
code in a new file, "partition.c" in the board directory.
board Makefiles updated to use the file.
The dataflash partitions are aligned on sector/page boundaries.
The CONFIG_NEW_DF_PARTITION was used to create named partitions
This is now the default operation, and the CONFIG variable is removed.
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
There are two NAND entries with ID 0xDC and this obviously causes problems.
In the kernel, they punted the first entry, so we should do the same.
See this upstream e-mail for more info:
http://lists.infradead.org/pipermail/linux-mtd/2007-July/018795.html
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
It should access with 16-bit instead of 8-bit
Now it uses the generic memcpy with 8-bit access. It means it reads wrong data from OneNAND.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit
series require different addresses for buffered write commands. Define a
configuration option to support buffered writes on those chips. A more
elegant solution would be to automatically detect those chips by parsing
their CFI records, but that would require introduction of a fixup table
into the cfi_flash driver.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
DataFlash partition information has become a mess. This patch
defines a single partition scheme for Atmel DataFlashes. This partition
scheme will be used by all AT91CAP9 and AT91SAM9 boards.
Signed-off-by: Stelian Pop <stelian@popies.net>
SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.
For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.
Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Add entry for 512Kx16 AMD flash to jedec_table.
Read out 16bit device id if chipwidth is 16bit.
Fixed coding style after Stefans feedback
Signed-off-by: Tor Krill <tor@excito.com>
Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array
using a NOR Flash interface. This on-chip integration enables system designers
to reduce external system logic and use high-density NAND Flash
in applications that would otherwise have to use more NOR components.
Flex-OneNAND enables users to configure to partition it into SLC and MLC areas
in more flexible way. While MLC area of Flex-OneNAND can be used to store data
that require low reliability and high density, SLC area of Flex-OneNAND
to store data that need high reliability and high performance. Flex-OneNAND
can let users take advantage of storing these two different types of data
into one chip, which is making Flex-OneNAND more cost- and space-effective.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
With this patch we don't need that many #ifdef's in the code. It moves
the subtraction into the macro and defines a NOP-macro when
CONFIG_FLASH_SHOW_PROGRESS is not defined.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Do not use uninitialized cmd_reset; issue both AMD and Intel reset
commands instead
From a short test, it looks like AMD-style flash roms treat *any* unknown
command write as a reset, at least when in CFI Query mode, so issuing the
Intel reset command to AMD-style flashs seems safe (from the small sample I
have), plus the 3-cycle magic sequence should kick the state machine into
the right state even without a reset command. Since the AMD-style flashs
require the unlock sequence for real operation, I chose to try the AMD reset
command first, so that Intel flashs do no see an invalid command prior to
the CFI query.
I have tested the patch on AM29LV320-style flashs from Fujitsu and Macronix,
plus Intel StrataFlash.
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This bug was detected on the LWMON5 target which has 2 Intel 16bit wide
flash chips connected to a 32bit wide port.
Signed-off-by: Stefan Roese <sr@denx.de>
The check for an sufficiently erased destination was missing in the
buffered write function of the cfi flash driver (when
CFG_FLASH_USE_BUFFER_WRITE is defined). This patch adds this check to that
writing to such a region will fail with the currect error message.
Signed-off-by: Stefan Roese <sr@denx.de>
Run fixups based on the JEDEC manufacturer ID independent of the
command set ID.
This changes current behaviour: Previously, geometry reversal for AMD
chips were done based on the command set ID, while they are now done
based on the JEDEC manufacturer and device ID.
Also add fixup for top-boot Atmel chips. A fixup is needed for
AT49BV6416(T) too, but since u-boot currently only reads the low byte
of the device ID, there's no way to tell it apart from AT49BV642D,
which should not have this fixup. Since AT49BV642D support is
necessary to get ATNGW100 board support into mainline, I've commented
out the fixup for now.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Move things like reading JEDEC IDs and fixing up geometry reversal
into separate functions. The geometry reversal fixup is now performed
by altering the qry structure directly, which makes the sector init
code slightly cleaner.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Read out the whole CFI Standard Query structure after successful cfi
identification. This allows subsequent code to access this information
directly without having to go through flash_read_uchar() and friends.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Use map_physmem() and unmap_physmem() to convert from physical to
virtual addresses. This gives the arch a chance to provide an uncached
mapping for flash accesses.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use
them to access the flash memory. This makes it clearer when the flash
is actually being accessed; merely dereferencing a volatile pointer
looks just like any other kind of access.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Reorder the functions in cfi_flash.c so that each function only uses
functions that have been defined before it. This allows the static
prototype declarations near the top to be eliminated and might allow
gcc to do a better job inlining functions.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This patch tries to keep all lines in the cfi_flash driver below 80
columns. There are a few lines left which don't fit this requirement
because I couldn't find any trivial way to break them (i.e. it would
take some restructuring, which I intend to do in a later patch.)
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The following patch adds support for non-CFI flash ROMS, by hooking into the
CFI flash code and using most of its code, as recently discussed here in the
thread "Mixing CFI and non-CFI flashs".
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Signed-off-by: Stefan Roese <sr@denx.de>
