Commit graph

67497 commits

Author SHA1 Message Date
Simon Glass
411e9eb88c w1: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
055efe5690 thermal: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
a00867b47a sf: Drop dm.h header file from spi_flash.h
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
2a64ada78c net: Drop dm.h header file from phy.h
This header file should not be included in other header files. Remove it
and use other headers and C inclusions instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
c2848cc2c3 fs: fs-loader: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
0e1fad4382 dm: core: Drop header files from dm/test.h
These header file should not be included in other header files. Remove
them and add to each individual file. Add test/test.h to test/ui.h since
that is a reasonable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
82a7697b5a dm: core: Drop dm.h header file from dm-demo.h
This header file should not be included in other header files. Remove it
and add it to the cmd file instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
54234592df mtd: spi: Drop SPI_XFER_MMAP*
These two defines are no-longer supported. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
340fd10e7b mtd: spi-mem: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
defce58181 wdt: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Also remove the other headers that are not needed, since the inline code
was removed in a recent commit:

   b4d9452c4 ("watchdog: move initr_watchdog() to wdt-uclass.c")

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
e567ec849a mtd: spi-nor: Tidy up error handling / debug code
The -ENODEV error value in spi_nor_read_id() is incorrect since there
clearly is a device - it just cannot be supported. Use -ENOMEDIUM instead
which has the virtue of being less common.

Fix the return value in spi_nor_scan().

Also there are a few printf() statements which should be debug() since
they bloat the code with unused strings at present. Fix those while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
f38a29997d spi: Allow separate control of SPI_FLASH_TINY for SPL/TPL
In some cases SPL needs to be able to erase but TPL just needs to read.
Allow these to have separate settings for SPI_FLASH_TINY.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Sagar Shrikant Kadam
ed50d3fae4 configs: reset: fu540: enable dm reset framework for SiFive
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
ea4e9570eb fu540: dtsi: add reset producer and consumer entries
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
d2e4398637 fu540: prci: use common reset indexes defined in binding header
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
ef9f65f389 dt-bindings: prci: add indexes for reset signals available in prci
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Anatolij Gustschin
3ce83ee012 video: ipuv3: fix framebuffer base address init with multiple IPUs
Since commit 7812bbdc37 ("video: Correctly handle multiple
framebuffers") the vidconsole output is missing on the primary
display on boards with two IPU units (all i.MX6Q/D based boards).
The base address of the allocated framebuffer is not correctly
programmed in the display controller. Fix it.

Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Soeren Moch <smoch@web.de>
2020-08-03 23:37:31 +02:00
Soeren Moch
645d39aea3 board: tbs2910: Fix video output with existing environments
Migration to DM_VIDEO changed the output device name (in stout, stderr)
from 'vga' to 'vidconsole'. This also was adapted in the default environment.
However, existing user defined environments still use 'vga'. Enable this
workaround to map the 'vga' name to 'vidconsole'. So we get HDMI video
output also with existing legacy environments.

Signed-off-by: Soeren Moch <smoch@web.de>
2020-08-03 23:36:50 +02:00
Stefan Roese
d071ff012e mips: octeon: Update EBB7304 defconfig
This patch enables the following options for the Octeon EBB7304 EVB:

- PCI & DM_PCI
- DM_SPI_FLASH & SPI flash device support
- SPI & Octeon SPI driver
- GPIO cmd support
- I2C cmd support

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:49 +02:00
Stefan Roese
1015540d70 mips: octeon: Update Octeon Kconfig
This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL
and DM_ETH are already selected.

Additionally the selections are now alphabetically sorted.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Stefan Roese
9044ed2c68 mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT node
Add the SPI flash DT node for the EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Stefan Roese
1032491904 mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT node
Add the Octeon SPI DT node to the dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Suneel Garapati
7853cc0598 drivers: spi: Add SPI controller driver for Octeon
Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-08-03 21:14:48 +02:00
Stefan Roese
a078c65172 mips: octeon: dts: Add Octeon clock driver DT nodes
This patch adds the DT nodes for the Octeon clock support via the
common clk_ API.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Stefan Roese
b113c9b570 clk: clk_octeon: Add simple MIPS Octeon clock driver
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC
family. Its for IO clock rate passing via DT in some of the Octeon
driver, like I2C. So that we don't need to use the non-mainline API
octeon_get_io_clock().

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
2020-08-03 21:11:41 +02:00
Stefan Roese
7ab932825d mips: octeon: dts: Add I2C DT nodes
Add I2C DT nodes to the Octeon dts / dtsi files.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Stefan Roese
fad5ec5ecd mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodes
Add the Octeon GPIO DT node to the dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Suneel Garapati
f7331c65b8 gpio: octeon_gpio: Add GPIO controller driver for Octeon
Add support for GPIO controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-08-03 21:11:41 +02:00
Heinrich Schuchardt
260ebed704 doc: qemu-mips build instructions
Correct the make commands for the defconfigs.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-03 20:29:55 +02:00
Wig Cheng
3e980a2d8b configs: pico-imx6: convert ethernet function to DM_ETH
Before enable _DM_ETH:
    Net:   FEC [PRIME]

After enable DM_ETH:
    Net:   eth0: ethernet@2188000

Here is the test commands:
    => dhcp
    BOOTP broadcast 1
    DHCP client bound to address 10.88.88.152 (146 ms)
    *** ERROR: `serverip' not set
    Cannot autoload with TFTPGET
    => ping 8.8.8.8
    Using ethernet@2188000 device
    host 8.8.8.8 is alive

Signed-off-by: Wig Cheng <wig.cheng@technexion.com>
2020-08-03 17:03:57 +02:00
Peng Fan
b297c0d707 imx8m: enlarge CONFIG_SYS_BOOTM_LEN
Enlarge CONFIG_SYS_BOOTM_LEN when booting FIT image with AArch32 mode
Linux kernel.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-08-03 17:03:57 +02:00
Niel Fourie
a1c6aed1de arm: imx6q: pcm058: Rework SPI NOR configuration
Enable CONFIG_SPL_DM_SPI_FLASH to be able to boot from SPI NOR,
modify the offset of U-boot proper in the SPI NOR, so the
difference in offset matches between SPL and U-boot matches that of
the SD Card, allowing u-boot-with-spl.imx to also be copied to SPI
NOR at an offset of 0x400. Update the README to reflect this
change.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-08-03 17:03:57 +02:00
Marek Vasut
1e7a69f661 ARM: imx: hab: panic on authentication failure
Instead of hang()ing the system and thus disallowing any automated
recovery possibility from a HAB authentication failure, panic() .
The panic() function can be configured to hang() the system after
printing an error message, however the default is to reset the
system instead.

This allows redundant boot to work correctly. In case the primary
or secondary image cannot be authenticated, the system reboots and
bootrom can try to start the other one.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-03 17:03:57 +02:00
Parthiban Nallathambi
10e959a1ca imx: Add MYiR Tech MYS-6ULX support
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based
on imx6ULL SoC from NXP and provision for expansion board. This
commit adds support only for SBC with NAND.

CPU:   Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 45C
Reset cause: WDOG
Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND
Board: MYiR MYS-6ULX 6ULL Single Board Computer
DRAM:  256 MiB
NAND:  256 MiB
MMC:   FSL_SDHC: 0
In:    serial@2020000
Out:   serial@2020000
Err:   serial@2020000
Net:   FEC0

Working:
 - Eth0
 - MMC/SD
 - NAND
 - UART 1
 - USB host

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-08-03 17:03:57 +02:00
Tom Rini
68941e3b2c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- ApolloLake: add u64 parameters support for FSP2 bindings
- ApolloLake: add missing parameters to support full configuration of
  the latest FSP MR6 release
- Append appropriate suffixes in various assembly codes
2020-08-03 10:25:47 -04:00
Tom Rini
4dc3ba568f Pull request for UEFI sub-system for efi-2020-10-rc2
This series comprises error corrections for the UEFI subsystem:
 
 * make the memory size reserved for the U-Boot stack customizable
   and reduce it for the MAIX board
 * correct build dependencies for UEFI unit test
 * enable read-only UEFI variable are enabled with the TEE backend
 * add 10 ms wait to sysreset to fix a problem with unit testing
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAl8li/IACgkQxIHbvCwF
 GsT2Ng/+Nvi034xRczd3Y4JiDf2eAHGlgTomtgtR+zVEKGA2bs5HHuG81Zf/56oU
 E3HHOk14FaAxbq+L5h0d8MusShxoQYxWTytlSUpyIiYyaqUAczkUxmcfpxTF/z0B
 LiuUGFAZZE53dvMTlbMydModLeKYf+4E1eGj+0PLF4Pxn6in15zZhz6QOXDZwo8E
 Ht2gVDjB0Br9GGAvIs3joy98PK9W3Q0i36/rGQ4jkJKOpEZCJorgvDQjOGgMWiin
 hGzg6AqoEFFfK7KFrMRYW2yWbnd8Mlo3+WsfsyeUnq7jVbPVY1oVvJxiz7Msg2Qd
 wWEAGuSg+aXgJULbxKqfG55j3k32LpheaUd8VNOZKJ2eu0anmx3/S/K8qNSGFdmu
 69scnf77xZSZHintjLY8SFvWAhNONCPcM3G8X/1mvn98hKIs1NBiRYD0DBSImQ76
 ewl7yyLIYStayFcpMn7fi//u6dKpNETXXIoAHuyAo/ol2wGMmjohgyn12vHuP5B0
 tvjzL42/6rJ1WzQEyZc50A6WoFPD4QEOq7BYznBiYdN3ACsZWiFvZGvrg6PAF1rC
 l20yD7Pq3uaVI4zvr9KyfOltHgn9KXiQkMz+o5BGNEp0gE67XD/vyRfspifH+8sv
 RARDLCiXDR0BfeNdzfXRede41wPPIP4+hNm2PX4FacptRucdPO8=
 =ysb+
 -----END PGP SIGNATURE-----

Merge tag 'efi-2020-10-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-10-rc2

This series comprises error corrections for the UEFI subsystem:

* make the memory size reserved for the U-Boot stack customizable
  and reduce it for the MAIX board
* correct build dependencies for UEFI unit test
* enable read-only UEFI variable are enabled with the TEE backend
* add 10 ms wait to sysreset to fix a problem with unit testing
2020-08-03 08:01:08 -04:00
Andy Shevchenko
940185910f x86: call32: Append appropriate suffixes
Assembler is not happy:

arch/x86/cpu/call32.S: Assembler messages:
arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'

Fix this by adding appropriate suffixes to the assembler commands.

Fixes: 6f92ed8f1a ("x86: Add a way to call 32-bit code from 64-bit mode")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Andy Shevchenko
549c6f47e6 x86: sipi_vector: Append appropriate suffixes
Assembler is not happy:

arch/x86/cpu/sipi_vector.S: Assembler messages:
arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'
arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'

Fix this by adding appropriate suffixes to the assembler commands.

Fixes: 45b5a37836 ("x86: Add multi-processor init")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Bernhard Messerklinger
a0186110af arch: x86: apl: Update FSP parameters
Add missing parameters to support full configuration of the latest FSP
MR6 release.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Bernhard Messerklinger
858e5a1a8b x86: apl: fsp_bindings: Add support for u64 parameters
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Wolfgang Wallner
491135805e x86: irq: Fix some typos
Fix some typos in arch/x86/include/asm/irq.h.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Marek Vasut
5f52d6e908 sh: r2dplus: Enable additional PCI ethernet devices
Enable these extra PCI ethernet devices, so they can be tested in CI.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:27 +02:00
Marek Vasut
3adaa25476 sh: r2dplus: Enable DM_SERIAL and DM_CLK
Switch r2dplus to DM and DT probing for serial and clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:27 +02:00
Marek Vasut
f70ca794be sh: r2dplus: Add SCIF1 to the basic DT
Add simple DT and clock bindings to r2dplus DT to permit U-Boot
to bind the SCIF driver via DT probing instead of hard-coded
config options.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:27 +02:00
Marek Vasut
3223ca99ee sh: Set gd->malloc_base if MALLOC_F_LEN is set
The gd->malloc_base must be set before the C runtime if the MALLOC_F_LEN
is non-zero, otherwise we hit assertion in dlmalloc.c initf_malloc(). So
set it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:26 +02:00
Marek Vasut
7bee46fd40 sh: r2dplus: Add pci enum to preboot
The ethernet on r2dplus is on PCI bus, enumerate the PCI early
to get the ethernet operational.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 17:09:59 +02:00
Marek Vasut
46a378b8e3 sh: r2dplus: Switch to DM ETH
Enable DM ethernet support for the board, now that rtl8139 is converted.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 17:09:59 +02:00
Walter Lozano
ae28d33cde mx6cuboxi: enable OF_PLATDATA
As both MMC and GPIO driver now supports OF_PLATDATA, enable it in
defconfig in order to reduce the SPL footprint. After applying this
setting the SPL reduction is 5 KB, which partially compensates the
increment due to DM.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-02 14:51:54 +02:00
Walter Lozano
24968d9e5f drivers: rename more drivers to match compatible string
Continuing with the approach in commit <addf358bac1d2bd0> rename
additional drivers to allow the OF_PLATDATA support.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-02 14:51:08 +02:00