Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.
* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
These changes were done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.
* Adds support for name to gpio conversion in s5p_gpio to enable
gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This sets up the linkage from the phydev back to the ethernet device. This
symptom of not doing this which I noticed was:
<NULL> Waiting for PHY auto negotiation to complete....
rather than:
dwmac.1c50000 Waiting for PHY auto negotiation to complete....
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Some functions in include/net.h are ported from
include/linux/etherdevice.h of Linux Kernel.
For ex.
is_zero_ether_addr()
is_multicast_ether_addr()
is_broadcast_ether_addr()
is_valid_ether_addr();
So, we should use the same function name as that of Linux Kernel,
eth_rand_addr(), for consistency.
Besides, eth_rand_addr() has been implemented as an inline function.
So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As some PHYs have non-standard PHY ID registers, PHY Id can't
be read correctly by current get_phy_id function, so we enable
get_phy_id redefinable to permit specific PHY driver having own
specific get_phy_id function.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before,
but used "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8035
to enable autonegotiation. Then removed the genphy_config_aneg() function.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
keystone serial hw support hw flow control. This patch
enables hw flow control for keystone EVMs as an optional
feature based on CONFIG_SERIAL_HW_FLOW_CONTROL.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
gd->bd->bi_baudrate is a copy of gd->baudrate.
Since baudrate is a common feature for all architectures,
keep gd->baudrate only.
It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
This patch adds support for the imx25 lcd display controller.
Signed-off-by: Thomas Diener <dietho@gmx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
The LTC3676 PMIC includes four DC/DC converters, and three 300mA
LDO Regulators (two Adjustable). The DC/DC converters are adjustable based
on a resistor devider (board-specific).
This adds support for the LTC3676 by creating a namespace unique init function
that uses the PMIC API to allocate a pmic and defines the registers.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Avoid uding pmic_init() as this forces the model of only allowing a
single PMIC driver to be built at a time.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
add a possibility to add a medium specific polltimeout
function. So it is possible to define different
poll timeouts.
Used on nand medium, for setting the DFU_MANIFEST_POLL_TIMEOUT
only on nand ubi partitions, which is currently the only
usecase.
Change-Id: If1db5f49b32d93fefa7481e8dfe5b7ccc0e65af4
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
comment in ep0_txstate() states:
"report completions as soon as the fifo's loaded; there's no win
in waiting till this last packet gets acked".
This is wrong for using dfu. In the dfu usecase we must send
a PollTimeout to the host, so the host can wait until the
U-Boot Code is ready for answering new usb requests. So the
answer which contains the PollTimeout must send *before*
U-Boot calls req->complete.
The req->complete is used in the dfu case for flushing the
medium, when entering DFU_STATE_dfuMANIFEST_SYNC state.
Change-Id: Ib2941119c72761e48e15fedbdad1ecce07ae0b3d
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
This patch contains an implementation of the fastboot protocol on the
device side and documentation. This is based on USB download gadget
infrastructure. The fastboot function implements the getvar, reboot,
download and reboot commands. What is missing is the flash handling i.e.
writting the image to media.
v3 (Rob Herring):
This is based on http://patchwork.ozlabs.org/patch/126798/ with the
following changes:
- Rebase to current mainline and updates for current gadget API
- Use SPDX identifiers for licenses
- Traced the history and added missing copyright to cmd_fastboot.c
- Use load_addr/load_size for transfer buffer
- Allow vendor strings to be optional
- Set vendor/product ID from config defines
- Allow Ctrl-C to exit fastboot mode
v4:
- Major re-write to use the USB download gadget. Consolidated function
code to a single file.
- Moved globals into single struct.
- Use puts and putc as appropriate.
- Added CONFIG_USB_FASTBOOT_BUF_ADDR and CONFIG_USB_FASTBOOT_BUF_SIZE to
set the fastboot transfer buffer.
v5:
- Add CONFIG option documentation to README
- Rebase using new downloader registration
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Now that the ci_udc driver supports allocating multiple requests per
endpoint, we can revert the special-case added by a022c1e13c "usb:
ums: use only 1 buffer for CI_UDC".
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify ci_ep_alloc_request() to return a dynamically allocated request
object, rather than a singleton that's part of the endpoint. This
requires moving various state from the endpoint structure to the request
structure, since we need one copy per request.
The "fast bounce buffer" b_fast is removed by this change rather than
moved to the request object. Instead, we enhance the bounce buffer logic
in ci_bounce()/ci_debounce() to keep the bounce buffer around between
request submissions. This avoids the need to allocate an arbitrarily-
sized bounce buffer up-front, yet avoids incurring the allocation
overhead each time a request is submitted.
A future enhancement would be to actually submit multiple requests to HW
at once. The Linux driver shows that this is possible. That might improve
throughput (depending on the USB protocol in use), since USB could be
performing a transfer to one HW buffer in parallel with whatever SW
actions U-Boot performs on another buffer. However, I have not made this
change as part of this patch, in order to keep SW changes related to
buffer management separate from any change in the way the HW is
programmed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
's/zynq_serial_initalize/zynq_serial_initialize/g'
serial_initialize is used by all serial drivers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Warnings:
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_init' was not declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_setbrg' was not declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_getc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_tstc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_putc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_puts' was not declared. Should it be static?
drivers/serial/serial_zynq.c:182:22: warning: symbol 'uart_zynq_serial0_device' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_init' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_setbrg' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_getc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_tstc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_putc' was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_puts' was not declared. Should it be static?
drivers/serial/serial_zynq.c:185:22: warning: symbol 'uart_zynq_serial1_device' was not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add missing header.
Warnings:
drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static?
drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The right correspondance between LCD margins and LCD timings is:
* upper margin -> vertical back porch
* lower margin -> vertical front porch
* left margin -> horizontal back porch
* right margin -> horizontal front porch
Signed-off-by: Josh Wu <josh.wu@atmel.com>
g_dnl_register() currently first attempts to register a composite
driver by name, and then saves the driver name once it's registered.
Internally to the registration code, g_dnl_do_config() is called and
attempts to compare the composite device's name with the list of known
device names. This fails since the composite device's name has not yet
been stored. This means that the first time "ums 0 0" is run, it fails,
but subsequent attempts succeed.
Re-order the name-saving and registration code to solve this.
Fixes: e5b834e07f51 ("USB: gadget: added a saner gadget downloader registration API")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Preprocessor definitions and hardcoded implementation selection in
g_dnl core were replaced by a linker list made of (usb_function_name,
bind_callback) pairs.
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
Previously offsets handled by dfu_fill_entity_mmc(), defined in boards'
CONFIG_DFU_ALT were treated as hexadecimal regardless of their prefix,
which sometimes led to confusion. This patch forces usage of explicit
numerical base prefixes.
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Tom Rini <trini@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
When user attempted to perform a raw write using DFU (vide
dfu_fill_entity_mmc) with MMC interface not initialized before,
get_mmc_blk_size() reported invalid (zero) block size - it wasn't
possible to write ie. a new u-boot image.
This commit fixes that by initializing MMC device before use in
dfu_fill_entity_mmc().
While fixing initialization sequence, I had to change about half of
dfu_fill_entity_mmc's body, so I refactored it on the way to make it,
IMHO, considerably more comprehensible.
Being left as dead code, get_mmc_blk_size() was removed.
Tested on Samsung Goni.
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Tom Rini <trini@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Former usb_cable_connected() patch broke compilation of boards which do
not support this feature.
I've renamed usb_cable_connected() to g_dnl_usb_cable_connected() and added
its default implementation to gadget downloader driver code. There's
only one driver of this kind and it's unlikely there'll be another, so
there's no point in keeping it in /common.
Previously this function was declared in usb.h. I've moved it, since
it's more appropriate to keep it in g_dnl.h - usb.h seems to be intended
for USB host implementation.
Existing code, confronted with default -EOPNOTSUPP return value,
continues as if the cable was connected.
CONFIG_USB_CABLE_CHECK was removed.
Change-Id: Ib9198621adee2811b391c64512f14646cefd0369
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Allow ci_udc.o to be built when using the new(?) USB gadget framework,
as enabled by CONFIG_USB_GADGET.
Note that this duplicates the Makefile entry for ci_udc.o, since it's
also included inside #ifdef CONFIG_USB_ETHER. I'm not sure what that
define means; perhaps an old style of Ethernet-specific USB gadget
implementation?
I wonder if the line that this patch adds shouldn't be outside all of
the ifdefs, so it stands on its own, similar to how e.g. epautoconf.o
is shared between the two?
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch updates the i.MX video driver to store the
frame-buffer address in the fb_base field of the global
data structure *gd.
By doing this, you can find the frame buffer address
using the 'bdinfo' command:
U-Boot > bdinfo
arch_number = 0x00000EB9
...
FB base = 0x4F35F1C0
This is very useful when debugging display connections.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
ci_udc.c allocates only a single buffer for each endpoint, which
ci_ep_alloc_request() returns as a hard-coded value rather than
dynamically allocating. Consequently, storage_common.c must limit
itself to using a single buffer at a time. Add a special case
to the definition of FSG_NUM_BUFFERS for this.
Another option would be to fix ci_ep_alloc_request() to dynamically
allocate the buffers like some/all(?) other device mode drivers do.
However, I don't think that ci_ep_queue() supports queueing up
multiple buffers either yet, and I'm not familiar enough with the
controller yet to implement that. As such, any attempt to use multiple
buffers simply results in data corruption and other errors.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra's USB controller appears to be a variant of the ChipIdea
controller; perhaps derived from it, or simply a different version of
the IP core to what U-Boot supports today.
In this variant, at least the following difference are present:
- Some registers are moved about.
- Setup transaction completion is reported in a separate 'epsetupstat'
register, rather than in 'epstat' (which still exists, perhaps for
other transaction types).
- USB connection speed is reported in a separate 'hostpc1_devlc'
register, rather than 'portsc'.
- The registers used by ci_udc.c begin at offset 0x130 from the USB
register base, rather than offset 0x140. However, this is handled
by the associated EHCI controller driver, since the register address
is stored in controller.ctrl->hcor.
Introduce define CONFIG_CI_UDC_HAS_HOSTPC to indicate which variant of
the controller should be supported. The "HAS_HOSTPC" part of this name
mirrors the similar "has_hostpc" field used by the Linux EHCI controller
core to represent the presence/absence of the hostpc1_devlc register.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
usb_gadget_register_driver() currently unconditionally programs PORTSC
to select a ULPI PHY. This is incorrect on at least the Tegra boards I
am testing with, which use a UTMI PHY for the OTG ports. Make the PHY
selection code conditional upon the specific EHCI controller that is in
use.
Ideally, I believe that the PHY initialization code should be part of
ehci_hcd_init() in the relevant EHCI controller driver, or some board-
specific function that ehci_hcd_init() calls.
For MX6, I'm not sure this PHY initialization code is correct even before
this patch, since ehci-mx6's ehci_hcd_init() already configures PORTSC to
a board-specific value, and it seems likely that the code in ci_udc.c is
incorrectly undoing this. Perhaps this is not an issue if the PHY
selection register bits aren't implemented on this instance of the MX6
USB controller?
ehci-mxs.c doens't appear to touch PORTSC, so this code is likely still
required there.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
At least drivers/usb/gadget/storage_common.c expects that ep->req.actual
contain the number of bytes actually transferred. (At least in practice,
I observed it failing to work correctly unless this was the case).
However, ci_udc.c modifies ep->req.length instead. I assume that .length
is supposed to represent the allocated buffer size, whereas .actual is
supposed to represent the actual number of bytes transferred. In the OUT
transaction case, this may happen simply because the host sends a smaller
packet than the max possible size, which is quite legal. In the IN case,
transferring fewer bytes than requested could presumably happen as an
error.
Modify handle_ep_complete() to write to .actual rather than modifying
.length.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ci_ep_queue() currently only fills in the page0/page1 fields in the
queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB
(page-aligned), then this prevents the HW from knowing where to write
the balance of the data.
Fix this by initializing all 5 pageN pointers, which allows up to
16KiB (potentially non-page-aligned) buffers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch remove always false (since we tested ret = 0) ternary operator
with ret value returned.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Commit 4a271cb1b4 doesn't take into account that fdtdec_setup_gpio()
returns success when the gpio passed to it is FDT_GPIO_NONE (no
gpio node found in the fdtdec_decode_gpio() call). This results in
calling gpio_direction_output() on invalid gpio. For this reason
executing "usb start" command on Arndale causes data abort in the
ehci-exynos driver.
Add the fdt_gpio_isvalid() check to fix that problem.
Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Add missing missing disconnect and unbind calls to the musb gadget driver's
usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail
to uninitialize and run a 2nd time.
Signed-off-by: Rob Herring <robh@kernel.org>
Allow a NULL table to be passed to usb_gadget_get_string for cases
when a string table may not be populated.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Since dfu read/write operations needs to be flushed manually,
writing to filesystem on MMC by thor was broken. MMC raw write
actually is working fine because current dfu_flush() function
writes filesystem only. This commit adds dfu_flush() to f_thor
and now filesystem write is working.
This change was tested on Trats2 board.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
In thor's download_tail() function, dfu_get_entity() is called
before each dfu_write() call and the returned entity pointers
are the same. So dfu_get_entity() can be called just once and
this patch changes this.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.
During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.
Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.
Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons
-On SoCs that have FMAN-v3H like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.
So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.
This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy
Signed-off-by: Nikhil Badola <B46172@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
The ordering of accesses to the rx & tx descriptors is important, yet
the send & recv functions accessed them via regular structure accesses.
This leaves the compiler with the opportunity to reorder those accesses
or to hoist them outside of loops. Prevent that from happening by using
readl & writel to access the descriptors. As a nice bonus, this removes
the need for the driver to care about endianness.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The prior accesses to the descriptor rings & init block via cached
memory had a few issues:
- The memory needs cache flushes or invalidation at the appropriate
times, but was not necessarily aligned on cache line boundaries.
This could lead to data being incorrectly lost or written back to
RAM at the wrong time.
- There are points where ordering of writes to the memory is
important, but because it's cached memory the pcnet controller
would see cache lines written back ordered by address. This could
occasionally lead to hardware seeing descriptors in an incorrect
state.
- Flushing the cache constantly is inefficient.
So, to avoid all of those issues simply access the descriptors & init
block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is
used to do this (retrieving an address in kseg1) as I could see no
existing generic solution. Since the MIPS Malta board is the only user
of the pcnet driver, hopefully this doesn't matter.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/lubbock/*
- Remove include/configs/lubbock.h
- Cleanup defined(CONFIG_LUBBOCK)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Ethernet driver configures the CPSW, SGMI and Phy and uses
the the Navigator APIs. The driver supports 4 Ethernet ports and
can work with only one port at a time.
Port configurations are defined in board.c.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Currently davinci spi driver supports only bus 0 cs 0.
This patch allows driver to support bus 1 and bus 2 with
configurable number of chip selects. Also defaults are
selected in a way to avoid regression on other platforms
that uses davinci spi driver and has only one spi bus.
Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.
This patch add support for keystone architecture and k2hk evm.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
- add davinci driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
This patch moves the davinci i2c_defs.h file to drivers.i2c directory.
It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs.
Not used "git mv" command to move the file because small part of
it with definitions specific for Davinci SOCs has to remain in the
arch/arm/include/asm/arch-davinci.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
This patch introduces a configurable mechanism to disable
subpage writes in the DaVinci NAND driver.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
This mainly converts the am335x_spl_bch driver to the "normal" format
which means a slight change to nand_info within the driver.
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.
Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.
The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Commit 2faf5fb82e introduced a regression that causes a data
abort when running scsi init followed by scsi reset.
There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.
Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.
Fixes: 2faf5fb82e (ahci: Fix cache align error messages)
Reported-by: Eli Nidam <elini@marvell.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.
2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
* Update of patch for change mmc interface by
Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
