Commit graph

82 commits

Author SHA1 Message Date
Simon Glass
7f926c9648 x86: Add support for building up an NHLT structure
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the device-tree bindings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-17 14:32:24 +08:00
Tom Rini
c87f9ce227 x86: Don't build some unused objects in TPL
In the future if we have separate symbols for DM_SPI_FLASH and
SPL_DM_SPI_FLASH we will not always have function declarations available
for some DM calls.  This in turn leads to build warnings but not
failures as the code isn't used and is discarded at link time.
Restructure things to not build code we won't use for TPL anyways.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-29 13:34:43 -04:00
Simon Glass
fb96deec50 x86: Don't include the BIOS emulator in TPL
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:18 +08:00
Simon Glass
e9de4a7cd3 x86: fsp: Move common dram functions into a common file
Most of the DRAM functionality can be shared between FSP1 and FSP2. Move
it into a shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:53:57 +08:00
Simon Glass
8331188615 x86: Rename existing FSP code to fsp1
Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.

Add a Kconfig which defines which version is in use.

Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:50:08 +08:00
Park, Aiden
7165fd584f x86: Add a common HOB library
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
Add a common HOB library in lib/hob.c and include/asm/hob.h.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Simon Glass
7c03caf6fa x86: Add a simple TPL implementation
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:18 +08:00
Heinrich Schuchardt
6b59607f10 x86: do not use i386 code for x86_64 memory functions
arch/x86/lib/string.c contains assembler implementations of memcpy(),
memmove(), and memset() written for i386. Don't use it on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Bin Meng
a0609a8d19 x86: acpi: Move APIs unrelated to ACPI tables generation to a separate library
acpi_find_fadt(), acpi_find_wakeup_vector() and enter_acpi_mode()
are something unrelated to ACPI tables generation. Move these to
a separate library.

This also fixes several style issues reported by checkpatch in the
original codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
4f1dacd43f x86: efi: Refactor the directory of EFI app and payload support
At present the EFI application and payload support codes in the x86
directory is distributed in a hybrid way. For example, the Kconfig
options for both app and payload are in arch/x86/lib/efi/Kconfig,
but the source codes in the same directory get built only for
CONFIG_EFI_STUB.

This refactors the codes by consolidating all the EFI support codes
into arch/x86/cpu/efi, just like other x86 targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
16dde8945e x86: efi: payload: Enforce toolchain to generate 64-bit EFI payload stub codes
Attempting to use a toolchain that is preconfigured to generate code
for the 32-bit architecture (i386), for example, the i386-linux-gcc
toolchain on kernel.org, to compile the 64-bit EFI payload does not
build. This updates the makefile fragments to ensure '-m64' is passed
to toolchain when building the 64-bit EFI payload stub codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Bin Meng
fcfc8a82b1 x86: Conditionally build the pinctrl_ich6 driver
The pinctrl_ich6 driver is currently unconditionally built for all
x86 boards. Let's use a Kconfig option to control the build.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Heinrich Schuchardt
f2560e2dea efi_loader: build CRT0 and RELOC on x86_64
The efi selftest and the hello application require CRT0 and RELOC to be
built.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-06-03 15:27:20 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
8e18f34c28 x86: Move commands from under arch/x86 to cmd/x86/
We only need to compile and link these files when building for full
U-Boot.  Move them to under cmd/x86/ to make sure they aren't linked in
and undiscarded due to u_boot_list_2_cmd_* being included).

Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-08 16:52:22 +08:00
Stefan Roese
aa7839b39c x86: lib: Implement standalone __udivdi3 etc instead of libgcc ones
This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.

The code taken from coreboot is authored from Vadim Bendebury
<vbendeb@chromium.org> on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).

I modified the code so that its checkpatch clean without any
functional changes.

[1] git://github.com/coreboot/coreboot.git

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Bin Meng
9f1fad1e36 x86: Add an early CMOS access library
This adds a library that provides CMOS (inside RTC SRAM) access
at a very early stage when driver model is not available yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
2017-05-17 17:11:46 +08:00
Bin Meng
3a34cae011 x86: acpi: Resume OS if resume vector is found
In an S3 resume path, U-Boot does everything like a cold boot except
in the last_stage_init() it jumps to the OS resume vector.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
2017-05-17 17:11:46 +08:00
Andy Shevchenko
ca0d29e4f0 x86: Introduce minimal PMU driver for Intel MID platforms
This simple PMU driver allows to tyrn power on and off for selected
devices. In particularly Intel Tangier needs to power on SDHCI
controllers in order to access to them during board initialization.

In the future it might be expanded to cover other Intel MID platforms,
that's why it's located under arch/x86/lib and called pmu.c.

Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-10 10:02:03 +08:00
Felipe Balbi
bb416465fd x86: Add SCU IPC driver for Intel MID platforms
Intel MID platforms have few microcontrollers inside SoC, one of them
is so called System Controller Unit (SCU).

Here is the driver to communicate with microcontroller.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-10 10:02:03 +08:00
Simon Glass
ca5114f9af x86: Don't try to boot Linux from SPL
Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing
in the bootm code until it is implemented.

Of course 32-bit U-Boot still supports booting into both 32- and 64-bit
kernels.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Simon Glass
e1b610b084 x86: Don't build 32-bit efi files on x86_64
These cannot be built in this mode, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Simon Glass
05cbd985c0 x86: Don't try to run the VGA BIOS in 64-bit mode
This is not supported, so disable it for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Simon Glass
4bbc02454f x86: Add an SPL implementation
SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping
to it. Call the existing init routines in order to accomplish this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Alexander Graf
95b62b2e28 efi_loader: Allow to compile helloworld.efi w/o bundling it
Today we can compile a self-contained hello world efi test binary that
allows us to quickly verify whether the EFI loader framwork works.

We can use that binary outside of the self-contained test case though,
by providing it to a to-be-tested system via tftp.

This patch separates compilation of the helloworld.efi file from
including it in the u-boot binary for "bootefi hello". It also modifies
the efi_loader test case to enable travis to pick up the compiled file.
Because we're now no longer bloating the resulting u-boot binary, we
can enable compilation always, giving us good travis test coverage.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-27 09:53:39 -05:00
Simon Glass
5bd828b532 efi: x86: Adjust EFI files support efi_loader
Add compiler flags and make a few minor adjustments to support the efi
loader.

Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Add Kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-14 23:24:04 +01:00
Simon Glass
2dcd4e9ee1 x86: Move efi .S files into the 'lib' directory
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-14 23:24:04 +01:00
Simon Glass
65e4c0b168 x86: efi: Add EFI loader support for x86
Add the required pieces to support the EFI loader on x86.

Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI application
is supported. If a 64-bit kernel must be booted, U-Boot supports this
directly using FIT (see doc/uImage.FIT/kernel.its). U-Boot can act as a
payload for both 32-bit and 64-bit EFI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-10-19 09:01:53 +02:00
Alexander Graf
4b6dddc294 x86: Move smbios generation into arch independent directory
We will need the SMBIOS generation function on ARM as well going forward,
so let's move it into a non arch specific location.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-19 09:01:50 +02:00
Bin Meng
548344912f x86: Compile coreboot_table.c only for SeaBIOS
coreboot_table.c only needs to be built when SeaBIOS is used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Miao Yan
34865a65c4 x86: qemu: fix ACPI Kconfig options
CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.

But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Simon Glass
7ac99be6e2 x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Bin Meng
26f9a9b73a x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
5c884420a5 x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:24 +08:00
Miao Yan
fa287b1580 x86: qemu: add the ability to load and link ACPI tables from QEMU
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Simon Glass
5544757ce9 dm: x86: Add a northbridge uclass
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
ca831f4933 dm: Expand the uclass for Platform Controller Hubs (PCH)
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Bin Meng
7030f27ef3 x86: tsc: Move tsc_timer.c to drivers/timer
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
da3fe24759 x86: Rename pcat_ to i8254 and i8259 accordingly
Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:18 -08:00
Bin Meng
f6220f1a86 x86: Move mrccache.[c|h] to a common place
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
62716ebb75 x86: fsp: Make hob command a sub-command to fsp
Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
721e992a8a x86: Add SMBIOS table support
System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
59ec719df6 x86: Move install_e820_map() out of zimage.c
install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Saket Sinha
867bcb63e7 x86: Generate a valid ACPI table
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.

Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:13 -07:00
Simon Glass
8e36650875 x86: Add helper code for running from EFI
When U-Boot is running from EFI some of the x86 init is replaced with
EFI-specific init. For example, since DRAM has already been set up, we only
need to find it, not init it. Add these functions so that boards can easily
allow booting from EFI if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
b997abd3f0 x86: Support building the EFI stub
Add support for building a 32/64-bit EFI stub for x86. This involves
building the startup and relocation code for either i386 or x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Bin Meng
7f5df8d42d x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Simon Glass
6388e35725 x86: Add support for the Simple Firmware Interface (SFI)
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:33 -06:00
Bin Meng
b5b6b01960 x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
5e2400e8f8 x86: Write configuration tables in last_stage_init()
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00