3 commits

Author	SHA1	Message	Date
Marek Vasut	29aa439759	arm: socfpga: Fix ArriaV SoCDK PLL config ... Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>	2015-08-23 11:56:21 +02:00
Marek Vasut	f6badb0d89	arm: socfpga: Switch to filtered QTS files ... Signed-off-by: Marek Vasut <marex@denx.de>	2015-08-23 11:56:20 +02:00
Marek Vasut	f089240128	arm: socfpga: Split Altera socfpga into AV and CV SoCDK ... The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>	2015-08-23 11:56:19 +02:00

Renamed from board/altera/socfpga/qts/pll_config.h (Browse further)