Commit graph

32 commits

Author SHA1 Message Date
Simon Glass
8909066199 dm: core: Drop ofnode_is_available()
This function is also available as ofnode_is_enabled(), so use that
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:31 -04:00
Peter Robinson
b5cf255f73 pci: tegra: Update error prints with new lines
Add new lines to make errorr messages easier to read.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:00 -07:00
Pali Rohár
d7b904092d pci: Add defines for normal and subtractive PCI bridges
Add following two new PCI class codes defines into pci_ids.h include file:

  PCI_CLASS_BRIDGE_PCI_NORMAL
  PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE

And use these defines in all U-Boot code for describing PCI class codes for
normal and subtractive PCI bridges.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-25 13:35:50 -04:00
Pali Rohár
86be29e9d9 pci: tegra: Use PCI_CONF1_EXT_ADDRESS() macro
PCI tegra driver uses extended format of Config Address for PCI
Configuration Mechanism #1 but with cleared Enable bit.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing
PCI_CONF1_ENABLE bit and remove old custom driver address function.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Simon Glass
d1998a9fde dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
c4e72c4ad8 dm: pci: Update the PCI read_config() method to const dev *
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Marcel Ziswiler
355560d588 pci: tegra: introduce weak tegra_pcie_board_port_reset() function
Introduce a weak tegra_pcie_board_port_reset() function by default
calling the existing tegra_pcie_port_reset() function. Additionally add
a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe
port index if required. This allows overriding the PCIe port reset
functionality from board specific code as e.g. required for Apalis T30
and Apalis TK1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:21 -07:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Tuomas Tynkkynen
be0105bc1e pci: tegra: Remove unused field 'hose' from struct tegra_pcie
This field is no longer used since the DM conversion. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Simon Glass
68f0081139 dm: tegra: pci: Convert to livetree
Update the tegra pci driver to support a live device tree. Fix the check
for nvidia,num-lanes so that an error will actually be detected.

Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Simon Glass
df87e6b1b8 libfdt: Sync fdt_for_each_subnode() with upstream
The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Update to drivers/power/pmic/palmas.c:
Signed-off-by: Keerthy <j-keerthy@ti.com>

Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
2016-10-13 14:10:32 -06:00
Stephen Warren
bbc5b36b25 pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
f39a6a3277 pci: tegra: actually program REFCLK_CFG* on recent SoCs
On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.

For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 11:14:32 -07:00
Stephen Warren
3cfc6be4a8 pci: tegra: correctly program PADS_REFCLK registers
The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 11:14:32 -07:00
Stephen Warren
f5c6db84e7 pci: tegra: fix DM conversion issues on Tegra20
Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:

1) The PCI_CLASS value is wrong in HW.

This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.

2) Accessing devices other than dev 1 causes a data abort.

Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.

I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.

Fixes: e81ca88451 ("dm: tegra: pci: Convert tegra boards to driver model for PCI")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-04 13:31:04 -07:00
Simon Glass
dfa71e9fcb tegra: Report errors from PCI init
This function can fail, so be sure to report any errors that occur.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:32:44 -06:00
Simon Glass
e81ca88451 dm: tegra: pci: Convert tegra boards to driver model for PCI
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Stephen Warren
d9eda6c441 pci: tegra: add/enable support for Tegra210
This needs a separate compatible value from Tegra124 since the new HW
version has bugs that would prevent a driver for previous HW versions
from operating at all.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
Stephen Warren
a02e263548 pci: tegra: call tegra_pcie_board_init() earlier
The board PCI setup code may control regulators that are required simply
to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move
the call to this function earlier so that all board-provided resources
are ready early enough for everything to work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
Stephen Warren
514e19138a pci: tegra: implement PCA enable workaround
Tegra210's PCIe controller has a bug that requires the PCA (performance
counter) feature to be enabled. If this isn't done, accesses to device
configuration space will hang the chip for tens of seconds. Implement
the workaround.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
Stephen Warren
223ddbcb09 pci: tegra: use #address-/size-cells from DT
The number of cells used by each entry in the DT ranges property is
determined by the #address-cells/#size-cells properties. Fix the code
to respect this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
Stephen Warren
bec05246f6 pci: tegra: clip RAM size to 32-bits
Tegra peripherals can generally access a 32-bit physical address space,
and I believe this applies to PCIe. Clip the PCI region that refers to
DRAM so it fits into 32-bits to avoid issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
York Sun
fdb9f349be lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
2015-08-06 07:31:13 -06:00
Sjoerd Simons
053b86e6d8 pci: tegra: Fix port information parsing
commit a62e84d7b1 incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).

With this patch i can successfully network boot my jetson tk1

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2015-01-23 17:25:30 -07:00
Bin Meng
a62e84d7b1 fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13 07:24:40 -08:00
Thierry Reding
f315828b0d pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00