Commit graph

11508 commits

Author SHA1 Message Date
Tom Rini
a6d4cd4778 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-05-08 15:44:44 -04:00
Lokesh Vutla
ee3c6532be ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00
Lokesh Vutla
c5f177debc ARM: k2g: Add support for dynamic programming of PLL based on SYSCLK
K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00
Nisal Menuka
8776350d87 Add ARM errata workaround 852421 and 852423 for Cortex-A17
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.

Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
2017-05-08 11:57:36 -04:00
maxims@google.com
d5c16d0093 aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
defb184904 aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
3b95902d47 aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.

The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.

The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.

So, the network driver would only need to enable these clocks, no need
to configure the rate.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
4999bb06cc aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:34 -04:00
maxims@google.com
4f0e44e466 aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:33 -04:00
maxims@google.com
99f8ad7321 aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.

To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.

Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.

These were the only users of the old Watchdog API, so that API is
removed.

This all is done in one change to avoid having to maintain dual API for
watchdog in between.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:32 -04:00
maxims@google.com
c93adc08f3 aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:32 -04:00
maxims@google.com
858d497629 aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:

rst: reset-controller {
    compatible = "aspeed,ast2500-reset";
    aspeed,wdt = <&wdt1>;
}

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:32 -04:00
maxims@google.com
413353b30b aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:31 -04:00
maxims@google.com
1eb0a464b7 aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:31 -04:00
maxims@google.com
0753bc2d30 dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:30 -04:00
maxims@google.com
17c5fb1953 aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:30 -04:00
Vikas Manocha
f22f3dc996 ARM: DT: STM32F746: add u-boot, dm-pre-reloc property to sub nodes
This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.

Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:57:30 -04:00
Pau Pajuelo
09533e5de7 igep003x: Add support for IGEP SMARC AM335x
The IGEP SMARC AM335x is an industrial processor module with
following highlights:

  o AM3352 TI processor (Up to AM3359)
  o Cortex-A8 ARM CPU
  o SMARC form factor module
  o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
  o WiFi a/b/g/n and Bluetooth v4.0 on-board
  o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes

Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:27 -04:00
Ladislav Michl
a96c08f509 igep0033: Rename to igep003x
Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:26 -04:00
Ladislav Michl
bf86392251 ARM: am33xx: define BOOT_DEVICE_ONENAND
am33xx does not support OneNAND, but we need this define anyway
to let UBI SPL code compile.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:25 -04:00
Ladislav Michl
df9f07fa3d ARM: am33xx: fix typo in spl.h
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:25 -04:00
Vikas Manocha
97c2093236 stm32f7: add support for stm32f769 disco board
This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.

To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only difference is to pass "DEVICE_TREE=stm32f769-disco".

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:24 -04:00
Vikas Manocha
bd4a985f50 stm32f7: move board specific pin muxing to dts
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:24 -04:00
Vikas Manocha
bfea69ad27 stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.

Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:22 -04:00
Vikas Manocha
2f80a9f72e stm32f746: to switch on user LED1 & read user button
All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:21 -04:00
Vikas Manocha
280057bd7d stm32f7: use stm32f7 gpio driver supporting driver model
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:21 -04:00
Vikas Manocha
d33a6a2f06 ARM: DT: stm32f7: add gpio device tree nodes
Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:20 -04:00
Vikas Manocha
774171020b dm: gpio: Add driver for stm32f7 gpio controller
This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:57:02 -04:00
Vikas Manocha
6c9a10034a stm32f7: sdram: use sdram device tree node to configure sdram controller
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:05 -04:00
Vikas Manocha
d0b24c1aa9 stm32f7: use clock driver to enable sdram controller clock
This patch also removes the sdram/fmc clock enable from board specific
code.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:04 -04:00
Vikas Manocha
fd198ee1a8 ARM: DT: stm32f7: add sdram pin contol node
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:03 -04:00
Vikas Manocha
890bafd752 stm32f7: use clock driver to enable qspi controller clock
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:38:41 -04:00
Vikas Manocha
5bf5250e9d spl: make image arg or fdt blob address reconfigurable
At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-08 11:38:40 -04:00
Uri Mashiach
67566ab66b arm: dra7xx: move CONFIG_DRA7XX to Kconfig
The symbol CONFIG_DRA7XX is needed for Kconfig conditions.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:38:35 -04:00
xypron.glpk@gmx.de
1275a44e2f arm64: mvebu: incorrect check of fdt address cells
In dram_init_banksize there seems to be a typo concerning
a plausibility check of the fdt.
Testing sc > 2 twice does not make any sense.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-05-05 16:45:56 -04:00
Icenowy Zheng
9946631a0f sunxi: add clock configuration of R40 sata
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).

Add clock configuration of R40 SATA.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-02 09:21:09 +02:00
Masahiro Yamada
af83a604b3 ARM: sunxi: use imply instead of bare default y in Kconfig
Fix annoying config redefines in SoC/board level Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-02 09:20:42 +02:00
Masahiro Yamada
3abfd887e8 ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/Kconfig
For the consistent location of SoC-level Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-02 09:20:30 +02:00
Tom Rini
26d61195f8 fdt: Move fdt_fixup_ethernet to a common place
With 3f66149d9f we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup.  On ARM however we largely relied on this call.  Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location.  Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d9f ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-01 09:11:59 -04:00
Simon Glass
3bd25cb512 Convert CONFIG_CMD_DIAG to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_DIAG

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_DIAG on some keymile configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:41:01 -04:00
Simon Glass
d569c95ec0 Convert CONFIG_CMD_DEKBLOB to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_DEKBLOB

Note: This option does not seem to actually be enabled by any board.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply under SECURE_BOOT for mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:41:00 -04:00
Simon Glass
80e44cfe10 fs: Kconfig: Add a separate option for FS_CRAMFS
Rather than using CMD_CRAMFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CRAMFS
support without the command, if desired, which reduces U-Boot's size
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:59 -04:00
Simon Glass
9707274718 fs: Convert CONFIG_CMD_CRAMFS to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_CRAMFS

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:59 -04:00
Simon Glass
d315628edb Convert CONFIG_CMD_CLK to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_CLK

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CLK on ARCH_ZYNQ]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:58 -04:00
Simon Glass
854fcd5537 Convert CONFIG_CMD_CHIP_CONFIG to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_CHIP_CONFIG

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 13:40:57 -04:00
Simon Glass
deb9599915 fs: Kconfig: Add a separate config for FS_CBFS
Rather than using CMD_CBFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CBFS
support without the command, if desired, which reduces U-Boot's size
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:57 -04:00
Simon Glass
d66a10fc00 fs: Convert CONFIG_CMD_CBFS to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_CBFS

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:56 -04:00
Simon Glass
218257b01a Convert CONFIG_CMD_BMODE to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_BMODE

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make this default y and depend on mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 10:30:06 -04:00
Simon Glass
c04b9b3440 Convert CONFIG_CMD_BLOB to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_BLOB

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add imply CMD_BLOB under CHAIN_OF_TRUST]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 10:30:03 -04:00
Simon Glass
56aceaf282 power: Rename CONFIG_AS3722_POWER to CONFIG_PMIC_AS3722
Before converting this to Kconfig, rename it to match the other PMICs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 10:29:47 -04:00