This patch adds support for the CPLD GPIO bus found on some LaCie boards
(as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO bus
exposes two registers (address and data). Each of this register is made
up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD
that the registers have been updated.
Mostly this bus is used to configure the LEDs on LaCie boards.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch adds support for the LaCie boards Network Space v2 (Lite and
Mini). This two boards are derived from the Network Space v2 and a lot
of hardware caracteristics are shared.
- CPU: Marvell 88F6192 800Mhz
- SDRAM memory: 128MB DDR2 200Mhz
- 1 SATA port: internal
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- i2c EEPROM: 512 bytes (24C04 type)
- 2 USB2 ports (Lite only): host and host/device
- 1 push button
- 1 SATA LED (bi-color, blue and red)
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always
returns 8 for the PHY address. It is the reset value for the PHY
Address Register. Obviously, this default value could be incorrect.
Moreover, as the PHY address is well known, there is no need to
auto-detect it.
Now, the PHY address must given as a parameter to the PHY initialization
function. Additionally this patch also fixes some aesthetic issues.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch groups together all the common functions for LaCie boards:
Ethernet PHY and MAC address initializations.
Moreover the configurations for LaCie Kirkwood boards are merged into
a single file: include/configs/lacie_kw.h
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
