Commit graph

743 commits

Author SHA1 Message Date
Albert ARIBAUD
10e167329b Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/Makefile
2013-06-08 14:35:10 +02:00
Alison Wang
bcb6e9023a net: fec_mxc: Add support for Vybrid VF610
This patch adds FEC support for Vybrid VF610 platform.

In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Suresh Gupta
16d88f415a Enable XAUI interface for B4860QDS
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Shaohui Xie
d54097b6c1 net/phy: fix select line for TN80xx
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Tom Rini
fb651b10d4 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2013-05-15 08:41:04 -04:00
Masahiro Yamada
bee0dc2fec smc911x: fix the timeout detection
If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-05-15 08:41:03 -04:00
Shaohui Xie
7794b1a7e6 net/phy: add VSC8574 support
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Shengzhou Liu
ae8a5d10f3 net/fm: fixup ethernet for mEMAC
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
York Sun
b62408464b powerpc/mpc85xx: Add T4160 SoC
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:29 -05:00
Shaohui Xie
944b6ccf1b Fman/t4240: some fix for 10G XAUI
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:26 -05:00
Marek Vasut
e6c5ab28c7 blackfin: The buf variable in bfin_mac.c is not used and produces warning,
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13 16:30:27 +08:00
Albert ARIBAUD
cac423a730 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-05-11 22:24:28 +02:00
Albert ARIBAUD
e825b100d2 Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-05-11 00:06:03 +02:00
Matt Porter
f485c8a35b phy: add support for ET1011C phys
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Matt Porter
f6f86a64ac cpsw: add support for TI814x slave_regs differences
TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Zang Roy-R61911
c5729f0b1f fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speed
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Michal Simek
f97d7e8be9 net: gem: Add support for phy autodetection
Autodetect phy if phyaddress is setup to -1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:26 +02:00
David Andrey
01fbf31042 net: gem: Preserve clk on emio interface
Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO

Do not enable emio for this standard board configuration for now.

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:24 +02:00
David Andrey
117cd4cc10 net: gem: Pass phy address to init
Pass the PHY address to the driver init to
allow parallel use of both interfaces

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:23 +02:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
058687597d net: gem: Do not initialize BDs again
BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.

This patch solves the problem with repeatable tftp transfers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:17 +02:00
Michal Simek
3b90d0afe5 net: gem: Simplify return path in zynq_gem_recv
Remove one return from the code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:16 +02:00
Michal Simek
986f00003c net: gem: Remove WRAP bit from TX buffer description
Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)

TRM: (Table 16-3: Tx Buffer Descriptor Entry)

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:14 +02:00
Michal Simek
1415107e46 net: phy: Define Marvell 88e1518 phy
This phy is used on zedboard (xilinx zynq platform).

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:13 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Tom Rini
98f92001b3 am33xx: Add required includes to some omap/am33xx code
- In arch/arm/cpu/armv7/omap-common/timer.c,
  drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
  that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
  <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
  as that is the only include which defines things the config uses.

Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Tom Rini
76b40ab41e Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 12:16:13 -04:00
Mugunthan V N
48ec529100 am335x: cpsw: optimize cpsw_send to increase network performance
Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-03-11 11:06:09 -04:00
Simon Glass
978226da5e net: Use new numeric setenv functions
Use setenv_ulong(), setenv_hex() and setenv_addr() in net/

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-28 19:09:23 -08:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Simon Glass
fefb098b18 ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
b28774966c ppc: Move mpc5xxx clocks to arch_global_data
Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Troy Kisky
fe428b909b net: fec_mxc: get phydev before fec_probe
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:51 +01:00
Troy Kisky
4dc27eed52 net: fec_mxc: only call phy_connect in fec_probe
This allows us to create the phydev before calling
fec_probe in later patch.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
ef8e3a3bbf net: fec_mxc: use fec_set_dev_name to set name
This allows us to create the phydev before calling
fec_probe in later patch.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
1adb406b01 phy: add phy_find_by_mask/phy_connect_dev
It is useful to be able to try a range of
possible phy addresses to connect.

Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
eef2448039 net: fec_mxc: have fecmxc_initialize call fecmxc_initialize_multi
Having only one call to fec_probe will ease the changing of its
parameters.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
575c5cc06f net: fec_mxc: change fec_mii_setspeed parameter
Only the hardware ethernet registers are needed
for this function, so don't pass the more general
structure. I'm trying to separate MII and fec.

This also fixes MX28 fec_mii_setspeed use on secondary ethernet port

This was found by inspection of the code and should be
checked on real hardware.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
09439c3197 net: fec_mxc: delete CONFIG_FEC_MXC_MULTI
It is more logical to test for CONFIG_FEC_MXC_PHYADDR
to determine whether to define the function fecmxc_initialize.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Albert ARIBAUD
0a16ea5933 mv88e61xx: refactor PHY and SWITCH level-code
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00
Yoshihiro Shimoda
e3bb3254f8 net: sh_eth: add support for SH7752
SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-12-15 12:28:24 -06:00
Michal Simek
b4b81e83f5 phy: Add support for Marvell 88E1118R
Marvell 88E1118R has different uid then 88E1118.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Andy Fleming <afleming@freescale.com>
CC: Zang Roy-R61911 <tie-fei.zang@freescale.com>
CC: Kumar Gala <galak@kernel.crashing.org>
2012-12-15 12:28:22 -06:00
Ruchika Gupta
776e66e8f1 e1000e : Correct Rx Threshold granularity
In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2012-12-15 12:28:21 -06:00
Yegor Yefremov
cdd0729ead am335x: cpsw: make phy address configurable
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2012-12-10 08:56:38 -07:00
Timur Tabi
d31e53b42c powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Kim Phillips
960d70c600 drivers/net/: sparse fixes
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00